1/*
2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8/ {
9	compatible = "arm,ffa-core-manifest-1.0";
10	#address-cells = <2>;
11	#size-cells = <1>;
12
13	attribute {
14		spmc_id = <0x8000>;
15		maj_ver = <0x1>;
16		min_ver = <0x1>;
17		exec_state = <0x0>;
18		load_address = <0x0 0xfd000000>;
19		entrypoint = <0x0 0xfd000000>;
20		binary_size = <0x80000>;
21	};
22
23	hypervisor {
24		compatible = "hafnium,hafnium";
25		vm1 {
26			is_ffa_partition;
27			debug_name = "cactus-primary";
28			load_address = <0xfe000000>;
29			vcpu_count = <8>;
30			mem_size = <1048576>;
31		};
32		vm2 {
33			is_ffa_partition;
34			debug_name = "cactus-secondary";
35			load_address = <0xfe100000>;
36			vcpu_count = <8>;
37			mem_size = <1048576>;
38		};
39		vm3 {
40			is_ffa_partition;
41			debug_name = "cactus-tertiary";
42			load_address = <0xfe200000>;
43			vcpu_count = <1>;
44			mem_size = <1048576>;
45		};
46	};
47
48	cpus {
49		#address-cells = <0x2>;
50		#size-cells = <0x0>;
51
52		CPU0:cpu@0 {
53			device_type = "cpu";
54			compatible = "arm,armv8";
55			reg = <0x0 0x0>;
56			enable-method = "psci";
57		};
58
59		/*
60		 * SPMC (Hafnium) requires secondary cpu nodes are declared in
61		 * descending order
62		 */
63		CPU7:cpu@700 {
64			device_type = "cpu";
65			compatible = "arm,armv8";
66			reg = <0x0 0x700>;
67			enable-method = "psci";
68		};
69
70		CPU6:cpu@600 {
71			device_type = "cpu";
72			compatible = "arm,armv8";
73			reg = <0x0 0x600>;
74			enable-method = "psci";
75		};
76
77		CPU5:cpu@500 {
78			device_type = "cpu";
79			compatible = "arm,armv8";
80			reg = <0x0 0x500>;
81			enable-method = "psci";
82		};
83
84		CPU4:cpu@400 {
85			device_type = "cpu";
86			compatible = "arm,armv8";
87			reg = <0x0 0x400>;
88			enable-method = "psci";
89		};
90
91		CPU3:cpu@300 {
92			device_type = "cpu";
93			compatible = "arm,armv8";
94			reg = <0x0 0x300>;
95			enable-method = "psci";
96		};
97
98		CPU2:cpu@200 {
99			device_type = "cpu";
100			compatible = "arm,armv8";
101			reg = <0x0 0x200>;
102			enable-method = "psci";
103		};
104
105		CPU1:cpu@100 {
106			device_type = "cpu";
107			compatible = "arm,armv8";
108			reg = <0x0 0x100>;
109			enable-method = "psci";
110		};
111	};
112
113	/* 32MB of TC_TZC_DRAM1_BASE */
114	memory@fd000000 {
115		device_type = "memory";
116		reg = <0x0 0xfd000000 0x2000000>;
117	};
118};
119