1# Copyright (c) 2021, Arm Limited. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4# 5 6ifeq ($(filter ${TARGET_PLATFORM}, 0 1),) 7 $(error TARGET_PLATFORM must be 0 or 1) 8endif 9 10CSS_LOAD_SCP_IMAGES := 1 11 12CSS_USE_SCMI_SDS_DRIVER := 1 13 14RAS_EXTENSION := 0 15 16SDEI_SUPPORT := 0 17 18EL3_EXCEPTION_HANDLING := 0 19 20HANDLE_EA_EL3_FIRST := 0 21 22# System coherency is managed in hardware 23HW_ASSISTED_COHERENCY := 1 24 25# When building for systems with hardware-assisted coherency, there's no need to 26# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 27USE_COHERENT_MEM := 0 28 29GIC_ENABLE_V4_EXTN := 1 30 31# GIC-600 configuration 32GICV3_SUPPORT_GIC600 := 1 33 34 35# Include GICv3 driver files 36include drivers/arm/gic/v3/gicv3.mk 37 38ENT_GIC_SOURCES := ${GICV3_SOURCES} \ 39 plat/common/plat_gicv3.c \ 40 plat/arm/common/arm_gicv3.c 41 42override NEED_BL2U := no 43 44override ARM_PLAT_MT := 1 45 46TC_BASE = plat/arm/board/tc 47 48PLAT_INCLUDES += -I${TC_BASE}/include/ 49 50# Common CPU libraries 51TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S 52 53# CPU libraries for TARGET_PLATFORM=0 54ifeq (${TARGET_PLATFORM}, 0) 55TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \ 56 lib/cpus/aarch64/cortex_x2.S 57endif 58 59# CPU libraries for TARGET_PLATFORM=1 60ifeq (${TARGET_PLATFORM}, 1) 61TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \ 62 lib/cpus/aarch64/cortex_makalu_elp_arm.S 63endif 64 65INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c 66 67PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \ 68 ${TC_BASE}/include/tc_helpers.S 69 70BL1_SOURCES += ${INTERCONNECT_SOURCES} \ 71 ${TC_CPU_SOURCES} \ 72 ${TC_BASE}/tc_trusted_boot.c \ 73 ${TC_BASE}/tc_err.c \ 74 drivers/arm/sbsa/sbsa.c 75 76 77BL2_SOURCES += ${TC_BASE}/tc_security.c \ 78 ${TC_BASE}/tc_err.c \ 79 ${TC_BASE}/tc_trusted_boot.c \ 80 lib/utils/mem_region.c \ 81 drivers/arm/tzc/tzc400.c \ 82 plat/arm/common/arm_tzc400.c \ 83 plat/arm/common/arm_nor_psci_mem_protect.c 84 85BL31_SOURCES += ${INTERCONNECT_SOURCES} \ 86 ${TC_CPU_SOURCES} \ 87 ${ENT_GIC_SOURCES} \ 88 ${TC_BASE}/tc_bl31_setup.c \ 89 ${TC_BASE}/tc_topology.c \ 90 drivers/cfi/v2m/v2m_flash.c \ 91 lib/utils/mem_region.c \ 92 plat/arm/common/arm_nor_psci_mem_protect.c 93 94# Add the FDT_SOURCES and options for Dynamic Config 95FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \ 96 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts 97FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 98TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 99 100# Add the FW_CONFIG to FIP and specify the same to certtool 101$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 102# Add the TB_FW_CONFIG to FIP and specify the same to certtool 103$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 104 105ifeq (${SPD},spmd) 106ifeq ($(ARM_SPMC_MANIFEST_DTS),) 107ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts 108endif 109 110FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 111TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 112 113# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 114$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG})) 115endif 116 117#Device tree 118TC_HW_CONFIG_DTS := fdts/tc.dts 119TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 120FDT_SOURCES += ${TC_HW_CONFIG_DTS} 121$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS))) 122 123# Add the HW_CONFIG to FIP and specify the same to certtool 124$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG})) 125 126override CTX_INCLUDE_AARCH32_REGS := 0 127 128override CTX_INCLUDE_PAUTH_REGS := 1 129 130override ENABLE_SPE_FOR_LOWER_ELS := 0 131 132override ENABLE_AMU := 1 133 134include plat/arm/common/arm_common.mk 135include plat/arm/css/common/css_common.mk 136include plat/arm/soc/common/soc_css.mk 137include plat/arm/board/common/board_common.mk 138