1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/console.h>
14 #include <lib/debugfs.h>
15 #include <lib/extensions/ras.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_tables_compat.h>
18 #include <plat/arm/common/plat_arm.h>
19 #include <plat/common/platform.h>
20 #include <platform_def.h>
21
22 #ifdef SPMC_AT_EL3
23 #include <services/spmc_svc.h>
24 #endif
25
26 /*
27 * Placeholder variables for copying the arguments that have been passed to
28 * BL31 from BL2.
29 */
30 static entry_point_info_t bl32_image_ep_info;
31 static entry_point_info_t bl33_image_ep_info;
32
33 #if !RESET_TO_BL31
34 /*
35 * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
36 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
37 */
38 CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows);
39 #endif
40
41 /* Weak definitions may be overridden in specific ARM standard platform */
42 #pragma weak bl31_early_platform_setup2
43 #pragma weak bl31_platform_setup
44 #pragma weak bl31_plat_arch_setup
45 #pragma weak bl31_plat_get_next_image_ep_info
46
47 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \
48 BL31_START, \
49 BL31_END - BL31_START, \
50 MT_MEMORY | MT_RW | MT_SECURE)
51 #if RECLAIM_INIT_CODE
52 IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
53 IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
54 IMPORT_SYM(unsigned long, __STACKS_END__, BL_STACKS_END_UNALIGNED);
55
56 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
57 ~(PAGE_SIZE - 1))
58 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
59 ~(PAGE_SIZE - 1))
60
61 #define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
62 BL_INIT_CODE_BASE, \
63 BL_INIT_CODE_END \
64 - BL_INIT_CODE_BASE, \
65 MT_CODE | MT_SECURE)
66 #endif
67
68 #if SEPARATE_NOBITS_REGION
69 #define MAP_BL31_NOBITS MAP_REGION_FLAT( \
70 BL31_NOBITS_BASE, \
71 BL31_NOBITS_LIMIT \
72 - BL31_NOBITS_BASE, \
73 MT_MEMORY | MT_RW | MT_SECURE)
74
75 #endif
76 /*******************************************************************************
77 * Return a pointer to the 'entry_point_info' structure of the next image for the
78 * security state specified. BL33 corresponds to the non-secure image type
79 * while BL32 corresponds to the secure image type. A NULL pointer is returned
80 * if the image does not exist.
81 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)82 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
83 {
84 entry_point_info_t *next_image_info;
85
86 assert(sec_state_is_valid(type));
87 next_image_info = (type == NON_SECURE)
88 ? &bl33_image_ep_info : &bl32_image_ep_info;
89 /*
90 * None of the images on the ARM development platforms can have 0x0
91 * as the entrypoint
92 */
93 if (next_image_info->pc)
94 return next_image_info;
95 else
96 return NULL;
97 }
98
99 /*******************************************************************************
100 * Perform any BL31 early platform setup common to ARM standard platforms.
101 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
102 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
103 * done before the MMU is initialized so that the memory layout can be used
104 * while creating page tables. BL2 has flushed this information to memory, so
105 * we are guaranteed to pick up good data.
106 ******************************************************************************/
arm_bl31_early_platform_setup(void * from_bl2,uintptr_t soc_fw_config,uintptr_t hw_config,void * plat_params_from_bl2)107 void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
108 uintptr_t hw_config, void *plat_params_from_bl2)
109 {
110 /* Initialize the console to provide early debug support */
111 arm_console_boot_init();
112
113 #if RESET_TO_BL31
114 /* There are no parameters from BL2 if BL31 is a reset vector */
115 assert(from_bl2 == NULL);
116 assert(plat_params_from_bl2 == NULL);
117
118 # ifdef BL32_BASE
119 /* Populate entry point information for BL32 */
120 SET_PARAM_HEAD(&bl32_image_ep_info,
121 PARAM_EP,
122 VERSION_1,
123 0);
124 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
125 bl32_image_ep_info.pc = BL32_BASE;
126 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
127
128 #if defined(SPD_spmd)
129 /* SPM (hafnium in secure world) expects SPM Core manifest base address
130 * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
131 * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
132 * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
133 * keep it in the last page.
134 */
135 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
136 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
137 #endif
138
139 # endif /* BL32_BASE */
140
141 /* Populate entry point information for BL33 */
142 SET_PARAM_HEAD(&bl33_image_ep_info,
143 PARAM_EP,
144 VERSION_1,
145 0);
146 /*
147 * Tell BL31 where the non-trusted software image
148 * is located and the entry state information
149 */
150 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
151
152 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
153 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
154
155 #else /* RESET_TO_BL31 */
156
157 /*
158 * In debug builds, we pass a special value in 'plat_params_from_bl2'
159 * to verify platform parameters from BL2 to BL31.
160 * In release builds, it's not used.
161 */
162 assert(((unsigned long long)plat_params_from_bl2) ==
163 ARM_BL31_PLAT_PARAM_VAL);
164
165 /*
166 * Check params passed from BL2 should not be NULL,
167 */
168 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
169 assert(params_from_bl2 != NULL);
170 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
171 assert(params_from_bl2->h.version >= VERSION_2);
172
173 bl_params_node_t *bl_params = params_from_bl2->head;
174
175 /*
176 * Copy BL33 and BL32 (if present), entry point information.
177 * They are stored in Secure RAM, in BL2's address space.
178 */
179 while (bl_params != NULL) {
180 if (bl_params->image_id == BL32_IMAGE_ID)
181 bl32_image_ep_info = *bl_params->ep_info;
182
183 if (bl_params->image_id == BL33_IMAGE_ID)
184 bl33_image_ep_info = *bl_params->ep_info;
185
186 bl_params = bl_params->next_params_info;
187 }
188
189 if (bl33_image_ep_info.pc == 0U)
190 panic();
191
192 #endif /* RESET_TO_BL31 */
193
194 # if ARM_LINUX_KERNEL_AS_BL33
195 /*
196 * According to the file ``Documentation/arm64/booting.txt`` of the
197 * Linux kernel tree, Linux expects the physical address of the device
198 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
199 * must be 0.
200 */
201 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
202 bl33_image_ep_info.args.arg1 = 0U;
203 bl33_image_ep_info.args.arg2 = 0U;
204 bl33_image_ep_info.args.arg3 = 0U;
205 # endif
206
207 #if defined(SPD_spmd) && !defined(SPMC_AT_EL3)
208 /*
209 * Hafnium in normal world expects its manifest address in x0, In CI
210 * configuration manifest is preloaded at 0x80000000(start of DRAM).
211 */
212 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
213 #endif
214 }
215
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)216 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
217 u_register_t arg2, u_register_t arg3)
218 {
219 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
220
221 /*
222 * Initialize Interconnect for this cluster during cold boot.
223 * No need for locks as no other CPU is active.
224 */
225 plat_arm_interconnect_init();
226
227 /*
228 * Enable Interconnect coherency for the primary CPU's cluster.
229 * Earlier bootloader stages might already do this (e.g. Trusted
230 * Firmware's BL1 does it) but we can't assume so. There is no harm in
231 * executing this code twice anyway.
232 * Platform specific PSCI code will enable coherency for other
233 * clusters.
234 */
235 plat_arm_interconnect_enter_coherency();
236 }
237
238 /*******************************************************************************
239 * Perform any BL31 platform setup common to ARM standard platforms
240 ******************************************************************************/
arm_bl31_platform_setup(void)241 void arm_bl31_platform_setup(void)
242 {
243 /* Initialize the GIC driver, cpu and distributor interfaces */
244 plat_arm_gic_driver_init();
245 plat_arm_gic_init();
246
247 #if RESET_TO_BL31
248 /*
249 * Do initial security configuration to allow DRAM/device access
250 * (if earlier BL has not already done so).
251 */
252 plat_arm_security_setup();
253
254 #if defined(PLAT_ARM_MEM_PROT_ADDR)
255 arm_nor_psci_do_dyn_mem_protect();
256 #endif /* PLAT_ARM_MEM_PROT_ADDR */
257
258 #endif /* RESET_TO_BL31 */
259
260 /* Enable and initialize the System level generic timer */
261 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
262 CNTCR_FCREQ(0U) | CNTCR_EN);
263
264 /* Allow access to the System counter timer module */
265 arm_configure_sys_timer();
266
267 /* Initialize power controller before setting up topology */
268 plat_arm_pwrc_setup();
269
270 #if RAS_EXTENSION
271 ras_init();
272 #endif
273
274 #if USE_DEBUGFS
275 debugfs_init();
276 #endif /* USE_DEBUGFS */
277 }
278
279 /*******************************************************************************
280 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
281 * standard platforms
282 * Perform BL31 platform setup
283 ******************************************************************************/
arm_bl31_plat_runtime_setup(void)284 void arm_bl31_plat_runtime_setup(void)
285 {
286 console_switch_state(CONSOLE_FLAG_RUNTIME);
287
288 /* Initialize the runtime console */
289 arm_console_runtime_init();
290
291 #if RECLAIM_INIT_CODE
292 arm_free_init_memory();
293 #endif
294
295 #if PLAT_RO_XLAT_TABLES
296 arm_xlat_make_tables_readonly();
297 #endif
298 }
299
300 #if RECLAIM_INIT_CODE
301 /*
302 * Make memory for image boot time code RW to reclaim it as stack for the
303 * secondary cores, or RO where it cannot be reclaimed:
304 *
305 * |-------- INIT SECTION --------|
306 * -----------------------------------------
307 * | CORE 0 | CORE 1 | CORE 2 | EXTRA |
308 * | STACK | STACK | STACK | SPACE |
309 * -----------------------------------------
310 * <-------------------> <------>
311 * MAKE RW AND XN MAKE
312 * FOR STACKS RO AND XN
313 */
arm_free_init_memory(void)314 void arm_free_init_memory(void)
315 {
316 int ret = 0;
317
318 if (BL_STACKS_END < BL_INIT_CODE_END) {
319 /* Reclaim some of the init section as stack if possible. */
320 if (BL_INIT_CODE_BASE < BL_STACKS_END) {
321 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
322 BL_STACKS_END - BL_INIT_CODE_BASE,
323 MT_RW_DATA);
324 }
325 /* Make the rest of the init section read-only. */
326 ret |= xlat_change_mem_attributes(BL_STACKS_END,
327 BL_INIT_CODE_END - BL_STACKS_END,
328 MT_RO_DATA);
329 } else {
330 /* The stacks cover the init section, so reclaim it all. */
331 ret |= xlat_change_mem_attributes(BL_INIT_CODE_BASE,
332 BL_INIT_CODE_END - BL_INIT_CODE_BASE,
333 MT_RW_DATA);
334 }
335
336 if (ret != 0) {
337 ERROR("Could not reclaim initialization code");
338 panic();
339 }
340 }
341 #endif
342
bl31_platform_setup(void)343 void __init bl31_platform_setup(void)
344 {
345 arm_bl31_platform_setup();
346 }
347
bl31_plat_runtime_setup(void)348 void bl31_plat_runtime_setup(void)
349 {
350 arm_bl31_plat_runtime_setup();
351 }
352
353 /*******************************************************************************
354 * Perform the very early platform specific architectural setup shared between
355 * ARM standard platforms. This only does basic initialization. Later
356 * architectural setup (bl31_arch_setup()) does not do anything platform
357 * specific.
358 ******************************************************************************/
arm_bl31_plat_arch_setup(void)359 void __init arm_bl31_plat_arch_setup(void)
360 {
361 const mmap_region_t bl_regions[] = {
362 MAP_BL31_TOTAL,
363 #if RECLAIM_INIT_CODE
364 MAP_BL_INIT_CODE,
365 #endif
366 #if SEPARATE_NOBITS_REGION
367 MAP_BL31_NOBITS,
368 #endif
369 ARM_MAP_BL_RO,
370 #if USE_ROMLIB
371 ARM_MAP_ROMLIB_CODE,
372 ARM_MAP_ROMLIB_DATA,
373 #endif
374 #if USE_COHERENT_MEM
375 ARM_MAP_BL_COHERENT_RAM,
376 #endif
377 {0}
378 };
379
380 setup_page_tables(bl_regions, plat_arm_get_mmap());
381
382 enable_mmu_el3(0);
383
384 arm_setup_romlib();
385 }
386
bl31_plat_arch_setup(void)387 void __init bl31_plat_arch_setup(void)
388 {
389 arm_bl31_plat_arch_setup();
390 }
391