1 /*
2 * Copyright (c) 2019, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <lib/mmio.h>
8
9 #include "s10_pinmux.h"
10
11 const uint32_t sysmgr_pinmux_array_sel[] = {
12 0x00000000, 0x00000001, /* usb */
13 0x00000004, 0x00000001,
14 0x00000008, 0x00000001,
15 0x0000000c, 0x00000001,
16 0x00000010, 0x00000001,
17 0x00000014, 0x00000001,
18 0x00000018, 0x00000001,
19 0x0000001c, 0x00000001,
20 0x00000020, 0x00000001,
21 0x00000024, 0x00000001,
22 0x00000028, 0x00000001,
23 0x0000002c, 0x00000001,
24 0x00000030, 0x00000000, /* emac0 */
25 0x00000034, 0x00000000,
26 0x00000038, 0x00000000,
27 0x0000003c, 0x00000000,
28 0x00000040, 0x00000000,
29 0x00000044, 0x00000000,
30 0x00000048, 0x00000000,
31 0x0000004c, 0x00000000,
32 0x00000050, 0x00000000,
33 0x00000054, 0x00000000,
34 0x00000058, 0x00000000,
35 0x0000005c, 0x00000000,
36 0x00000060, 0x00000008, /* gpio1 */
37 0x00000064, 0x00000008,
38 0x00000068, 0x00000005, /* uart0 tx */
39 0x0000006c, 0x00000005, /* uart 0 rx */
40 0x00000070, 0x00000008, /* gpio */
41 0x00000074, 0x00000008,
42 0x00000078, 0x00000004, /* i2c1 */
43 0x0000007c, 0x00000004,
44 0x00000080, 0x00000007, /* jtag */
45 0x00000084, 0x00000007,
46 0x00000088, 0x00000007,
47 0x0000008c, 0x00000007,
48 0x00000090, 0x00000001, /* sdmmc data0 */
49 0x00000094, 0x00000001,
50 0x00000098, 0x00000001,
51 0x0000009c, 0x00000001,
52 0x00000100, 0x00000001,
53 0x00000104, 0x00000001, /* sdmmc.data3 */
54 0x00000108, 0x00000008, /* loan */
55 0x0000010c, 0x00000008, /* gpio */
56 0x00000110, 0x00000008,
57 0x00000114, 0x00000008, /* gpio1.io21 */
58 0x00000118, 0x00000005, /* mdio0.mdio */
59 0x0000011c, 0x00000005 /* mdio0.mdc */
60 };
61
62 const uint32_t sysmgr_pinmux_array_ctrl[] = {
63 0x00000000, 0x00502c38, /* Q1_1 */
64 0x00000004, 0x00102c38,
65 0x00000008, 0x00502c38,
66 0x0000000c, 0x00502c38,
67 0x00000010, 0x00502c38,
68 0x00000014, 0x00502c38,
69 0x00000018, 0x00502c38,
70 0x0000001c, 0x00502c38,
71 0x00000020, 0x00502c38,
72 0x00000024, 0x00502c38,
73 0x00000028, 0x00502c38,
74 0x0000002c, 0x00502c38,
75 0x00000030, 0x00102c38, /* Q2_1 */
76 0x00000034, 0x00102c38,
77 0x00000038, 0x00502c38,
78 0x0000003c, 0x00502c38,
79 0x00000040, 0x00102c38,
80 0x00000044, 0x00102c38,
81 0x00000048, 0x00502c38,
82 0x0000004c, 0x00502c38,
83 0x00000050, 0x00102c38,
84 0x00000054, 0x00102c38,
85 0x00000058, 0x00502c38,
86 0x0000005c, 0x00502c38,
87 0x00000060, 0x00502c38, /* Q3_1 */
88 0x00000064, 0x00502c38,
89 0x00000068, 0x00102c38,
90 0x0000006c, 0x00502c38,
91 0x000000d0, 0x00502c38,
92 0x000000d4, 0x00502c38,
93 0x000000d8, 0x00542c38,
94 0x000000dc, 0x00542c38,
95 0x000000e0, 0x00502c38,
96 0x000000e4, 0x00502c38,
97 0x000000e8, 0x00102c38,
98 0x000000ec, 0x00502c38,
99 0x000000f0, 0x00502c38, /* Q4_1 */
100 0x000000f4, 0x00502c38,
101 0x000000f8, 0x00102c38,
102 0x000000fc, 0x00502c38,
103 0x00000100, 0x00502c38,
104 0x00000104, 0x00502c38,
105 0x00000108, 0x00102c38,
106 0x0000010c, 0x00502c38,
107 0x00000110, 0x00502c38,
108 0x00000114, 0x00502c38,
109 0x00000118, 0x00542c38,
110 0x0000011c, 0x00102c38
111 };
112
113 const uint32_t sysmgr_pinmux_array_fpga[] = {
114 0x00000000, 0x00000000,
115 0x00000004, 0x00000000,
116 0x00000008, 0x00000000,
117 0x0000000c, 0x00000000,
118 0x00000010, 0x00000000,
119 0x00000014, 0x00000000,
120 0x00000018, 0x00000000,
121 0x0000001c, 0x00000000,
122 0x00000020, 0x00000000,
123 0x00000028, 0x00000000,
124 0x0000002c, 0x00000000,
125 0x00000030, 0x00000000,
126 0x00000034, 0x00000000,
127 0x00000038, 0x00000000,
128 0x0000003c, 0x00000000,
129 0x00000040, 0x00000000,
130 0x00000044, 0x00000000,
131 0x00000048, 0x00000000,
132 0x00000050, 0x00000000,
133 0x00000054, 0x00000000,
134 0x00000058, 0x0000002a
135 };
136
137 const uint32_t sysmgr_pinmux_array_iodelay[] = {
138 0x00000000, 0x00000000,
139 0x00000004, 0x00000000,
140 0x00000008, 0x00000000,
141 0x0000000c, 0x00000000,
142 0x00000010, 0x00000000,
143 0x00000014, 0x00000000,
144 0x00000018, 0x00000000,
145 0x0000001c, 0x00000000,
146 0x00000020, 0x00000000,
147 0x00000024, 0x00000000,
148 0x00000028, 0x00000000,
149 0x0000002c, 0x00000000,
150 0x00000030, 0x00000000,
151 0x00000034, 0x00000000,
152 0x00000038, 0x00000000,
153 0x0000003c, 0x00000000,
154 0x00000040, 0x00000000,
155 0x00000044, 0x00000000,
156 0x00000048, 0x00000000,
157 0x0000004c, 0x00000000,
158 0x00000050, 0x00000000,
159 0x00000054, 0x00000000,
160 0x00000058, 0x00000000,
161 0x0000005c, 0x00000000,
162 0x00000060, 0x00000000,
163 0x00000064, 0x00000000,
164 0x00000068, 0x00000000,
165 0x0000006c, 0x00000000,
166 0x00000070, 0x00000000,
167 0x00000074, 0x00000000,
168 0x00000078, 0x00000000,
169 0x0000007c, 0x00000000,
170 0x00000080, 0x00000000,
171 0x00000084, 0x00000000,
172 0x00000088, 0x00000000,
173 0x0000008c, 0x00000000,
174 0x00000090, 0x00000000,
175 0x00000094, 0x00000000,
176 0x00000098, 0x00000000,
177 0x0000009c, 0x00000000,
178 0x00000100, 0x00000000,
179 0x00000104, 0x00000000,
180 0x00000108, 0x00000000,
181 0x0000010c, 0x00000000,
182 0x00000110, 0x00000000,
183 0x00000114, 0x00000000,
184 0x00000118, 0x00000000,
185 0x0000011c, 0x00000000
186 };
187
config_pinmux(handoff * hoff_ptr)188 void config_pinmux(handoff *hoff_ptr)
189 {
190 unsigned int i;
191
192 for (i = 0; i < 96; i += 2) {
193 mmio_write_32(S10_PINMUX_PIN0SEL +
194 hoff_ptr->pinmux_sel_array[i],
195 hoff_ptr->pinmux_sel_array[i+1]);
196 }
197
198 for (i = 0; i < 96; i += 2) {
199 mmio_write_32(S10_PINMUX_IO0CTRL +
200 hoff_ptr->pinmux_io_array[i],
201 hoff_ptr->pinmux_io_array[i+1]);
202 }
203
204 for (i = 0; i < 42; i += 2) {
205 mmio_write_32(S10_PINMUX_PINMUX_EMAC0_USEFPGA +
206 hoff_ptr->pinmux_fpga_array[i],
207 hoff_ptr->pinmux_fpga_array[i+1]);
208 }
209
210 for (i = 0; i < 96; i += 2) {
211 mmio_write_32(S10_PINMUX_IO0_DELAY +
212 hoff_ptr->pinmux_iodelay_array[i],
213 hoff_ptr->pinmux_iodelay_array[i+1]);
214 }
215
216 }
217
218