1 /*
2  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <drivers/delay_timer.h>
9 #include <lib/mmio.h>
10 
11 #define TIMER_BASE_ADDR 0x02B00000
12 
ls_get_timer(uint64_t start)13 uint64_t ls_get_timer(uint64_t start)
14 {
15 	return read_cntpct_el0() * 1000 / read_cntfrq_el0() - start;
16 }
17 
ls_timeus_get_value(void)18 static uint32_t ls_timeus_get_value(void)
19 {
20 	/*
21 	 * Generic delay timer implementation expects the timer to be a down
22 	 * counter. We apply bitwise NOT operator to the tick values returned
23 	 * by read_cntpct_el0() to simulate the down counter. The value is
24 	 * clipped from 64 to 32 bits.
25 	 */
26 	return (uint32_t)(~read_cntpct_el0());
27 }
28 
29 static const timer_ops_t ls_timer_ops = {
30 	.get_timer_value	= ls_timeus_get_value,
31 	.clk_mult		= 1,
32 	.clk_div		= 25,
33 };
34 
35 
36 /*
37  * Initialise the nxp layerscape on-chip free rolling us counter as the delay
38  * timer.
39  */
ls_delay_timer_init(void)40 void ls_delay_timer_init(void)
41 {
42 	uintptr_t cntcr =  TIMER_BASE_ADDR;
43 
44 	mmio_write_32(cntcr, 0x1);
45 
46 	timer_init(&ls_timer_ops);
47 }
48