1 /*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 #include <common/debug.h>
9 #include <common/runtime_svc.h>
10 #include <drivers/marvell/cache_llc.h>
11 #include <drivers/marvell/mochi/ap_setup.h>
12 #include <drivers/rambus/trng_ip_76.h>
13 #include <lib/smccc.h>
14
15 #include <marvell_plat_priv.h>
16 #include <plat_marvell.h>
17
18 #include "comphy/phy-comphy-cp110.h"
19 #include "secure_dfx_access/dfx.h"
20 #include "ddr_phy_access.h"
21 #include <stdbool.h>
22
23 /* #define DEBUG_COMPHY */
24 #ifdef DEBUG_COMPHY
25 #define debug(format...) NOTICE(format)
26 #else
27 #define debug(format, arg...)
28 #endif
29
30 /* Comphy related FID's */
31 #define MV_SIP_COMPHY_POWER_ON 0x82000001
32 #define MV_SIP_COMPHY_POWER_OFF 0x82000002
33 #define MV_SIP_COMPHY_PLL_LOCK 0x82000003
34 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
35 #define MV_SIP_COMPHY_DIG_RESET 0x82000005
36
37 /* Miscellaneous FID's' */
38 #define MV_SIP_DRAM_SIZE 0x82000010
39 #define MV_SIP_LLC_ENABLE 0x82000011
40 #define MV_SIP_PMU_IRQ_ENABLE 0x82000012
41 #define MV_SIP_PMU_IRQ_DISABLE 0x82000013
42 #define MV_SIP_DFX 0x82000014
43 #define MV_SIP_DDR_PHY_WRITE 0x82000015
44 #define MV_SIP_DDR_PHY_READ 0x82000016
45
46 /* TRNG */
47 #define MV_SIP_RNG_64 0xC200FF11
48
49 #define MAX_LANE_NR 6
50 #define MVEBU_COMPHY_OFFSET 0x441000
51 #define MVEBU_CP_BASE_MASK (~0xffffff)
52
53 /* Common PHY register */
54 #define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c
55
56 /* This macro is used to identify COMPHY related calls from SMC function ID */
57 #define is_comphy_fid(fid) \
58 ((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
59
is_cp_range_valid(u_register_t * addr)60 _Bool is_cp_range_valid(u_register_t *addr)
61 {
62 int cp_nr;
63
64 *addr &= MVEBU_CP_BASE_MASK;
65 for (cp_nr = 0; cp_nr < CP_NUM; cp_nr++) {
66 if (*addr == MVEBU_CP_REGS_BASE(cp_nr))
67 return true;
68 }
69
70 return false;
71 }
72
mrvl_sip_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)73 uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid,
74 u_register_t x1,
75 u_register_t x2,
76 u_register_t x3,
77 u_register_t x4,
78 void *cookie,
79 void *handle,
80 u_register_t flags)
81 {
82 u_register_t ret, read, x5 = x1;
83 int i;
84
85 debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
86 __func__, smc_fid, x1, x2, x3);
87
88 if (is_comphy_fid(smc_fid)) {
89 /* validate address passed via x1 */
90 if (!is_cp_range_valid(&x1)) {
91 ERROR("%s: Wrong smc (0x%x) address: %lx\n",
92 __func__, smc_fid, x1);
93 SMC_RET1(handle, SMC_UNK);
94 }
95
96 x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS;
97 x1 += MVEBU_COMPHY_OFFSET;
98
99 if (x2 >= MAX_LANE_NR) {
100 ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n",
101 __func__, smc_fid, x2);
102 SMC_RET1(handle, SMC_UNK);
103 }
104 }
105
106 switch (smc_fid) {
107
108 /* Comphy related FID's */
109 case MV_SIP_COMPHY_POWER_ON:
110 /* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
111 ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5);
112 SMC_RET1(handle, ret);
113 case MV_SIP_COMPHY_POWER_OFF:
114 /* x1: comphy_base, x2: comphy_index */
115 ret = mvebu_cp110_comphy_power_off(x1, x2, x3);
116 SMC_RET1(handle, ret);
117 case MV_SIP_COMPHY_PLL_LOCK:
118 /* x1: comphy_base, x2: comphy_index */
119 ret = mvebu_cp110_comphy_is_pll_locked(x1, x2);
120 SMC_RET1(handle, ret);
121 case MV_SIP_COMPHY_XFI_TRAIN:
122 /* x1: comphy_base, x2: comphy_index */
123 ret = mvebu_cp110_comphy_xfi_rx_training(x1, x2);
124 SMC_RET1(handle, ret);
125 case MV_SIP_COMPHY_DIG_RESET:
126 /* x1: comphy_base, x2: comphy_index, x3: mode, x4: command */
127 ret = mvebu_cp110_comphy_digital_reset(x1, x2, x3, x4);
128 SMC_RET1(handle, ret);
129
130 /* Miscellaneous FID's' */
131 case MV_SIP_DRAM_SIZE:
132 ret = mvebu_get_dram_size(MVEBU_REGS_BASE);
133 SMC_RET1(handle, ret);
134 case MV_SIP_LLC_ENABLE:
135 for (i = 0; i < ap_get_count(); i++)
136 llc_runtime_enable(i);
137
138 SMC_RET1(handle, 0);
139 #ifdef MVEBU_PMU_IRQ_WA
140 case MV_SIP_PMU_IRQ_ENABLE:
141 mvebu_pmu_interrupt_enable();
142 SMC_RET1(handle, 0);
143 case MV_SIP_PMU_IRQ_DISABLE:
144 mvebu_pmu_interrupt_disable();
145 SMC_RET1(handle, 0);
146 #endif
147 case MV_SIP_DFX:
148 if (x1 >= MV_SIP_DFX_THERMAL_INIT &&
149 x1 <= MV_SIP_DFX_THERMAL_SEL_CHANNEL) {
150 ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3);
151 SMC_RET2(handle, ret, read);
152 }
153 if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) {
154 ret = mvebu_dfx_misc_handle(x1, &read, x2, x3);
155 SMC_RET2(handle, ret, read);
156 }
157
158 SMC_RET1(handle, SMC_UNK);
159 case MV_SIP_DDR_PHY_WRITE:
160 ret = mvebu_ddr_phy_write(x1, x2);
161 SMC_RET1(handle, ret);
162 case MV_SIP_DDR_PHY_READ:
163 read = 0;
164 ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read);
165 SMC_RET2(handle, ret, read);
166 case MV_SIP_RNG_64:
167 if ((x1 % 2 + 1) > sizeof(read)/4) {
168 ERROR("%s: Maximum %ld random bytes per SMC call\n",
169 __func__, sizeof(read));
170 SMC_RET1(handle, SMC_UNK);
171 }
172 ret = eip76_rng_get_random((uint8_t *)&read, 4 * (x1 % 2 + 1));
173 SMC_RET2(handle, ret, read);
174 default:
175 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
176 SMC_RET1(handle, SMC_UNK);
177 }
178 }
179
180 /* Define a runtime service descriptor for fast SMC calls */
181 DECLARE_RT_SVC(
182 marvell_sip_svc,
183 OEN_SIP_START,
184 OEN_SIP_END,
185 SMC_TYPE_FAST,
186 NULL,
187 mrvl_sip_smc_handler
188 );
189