1/*
2 * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl31_entrypoint)
13
14
15MEMORY {
16	RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE
17	RAM2 (rwx): ORIGIN = TZRAM2_BASE, LENGTH = TZRAM2_SIZE
18}
19
20
21SECTIONS
22{
23    . = BL31_BASE;
24
25    ASSERT(. == ALIGN(2048),
26           "vector base is not aligned on a 2K boundary.")
27
28    __RO_START__ = .;
29    vector . : {
30        *(.vectors)
31    } >RAM
32
33    ASSERT(. == ALIGN(PAGE_SIZE),
34           "BL31_BASE address is not aligned on a page boundary.")
35
36    ro . : {
37        *bl31_entrypoint.o(.text*)
38        *(.text*)
39        *(.rodata*)
40
41	RODATA_COMMON
42
43        __RO_END_UNALIGNED__ = .;
44        /*
45         * Memory page(s) mapped to this section will be marked as read-only,
46         * executable.  No RW data from the next section must creep in.
47         * Ensure the rest of the current memory page is unused.
48         */
49        . = ALIGN(PAGE_SIZE);
50        __RO_END__ = .;
51    } >RAM
52
53    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
54           "cpu_ops not defined for this platform.")
55
56    /*
57     * Define a linker symbol to mark start of the RW memory area for this
58     * image.
59     */
60    __RW_START__ = . ;
61
62    DATA_SECTION >RAM
63
64#ifdef BL31_PROGBITS_LIMIT
65    ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.")
66#endif
67
68    STACK_SECTION >RAM
69    BSS_SECTION >RAM
70    __RW_END__ = __BSS_END__;
71
72    ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
73
74    XLAT_TABLE_SECTION >RAM2
75
76#if USE_COHERENT_MEM
77    /*
78     * The base address of the coherent memory section must be page-aligned (4K)
79     * to guarantee that the coherent data are stored on their own pages and
80     * are not mixed with normal data.  This is required to set up the correct
81     * memory attributes for the coherent data page tables.
82     */
83    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
84        __COHERENT_RAM_START__ = .;
85        /*
86         * Bakery locks are stored in coherent memory
87         *
88         * Each lock's data is contiguous and fully allocated by the compiler
89         */
90        *(bakery_lock)
91        *(tzfw_coherent_mem)
92        __COHERENT_RAM_END_UNALIGNED__ = .;
93        /*
94         * Memory page(s) mapped to this section will be marked
95         * as device memory.  No other unexpected data must creep in.
96         * Ensure the rest of the current memory page is unused.
97         */
98        . = ALIGN(PAGE_SIZE);
99        __COHERENT_RAM_END__ = .;
100    } >RAM2
101#endif
102
103    /*
104     * Define a linker symbol to mark end of the RW memory area for this
105     * image.
106     */
107    __BL31_END__ = .;
108
109    __BSS_SIZE__ = SIZEOF(.bss);
110#if USE_COHERENT_MEM
111    __COHERENT_RAM_UNALIGNED_SIZE__ =
112        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
113#endif
114
115    ASSERT(. <= TZRAM2_LIMIT, "TZRAM2 image has exceeded its limit.")
116}
117