1 /*
2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/cci.h>
14 #include <drivers/console.h>
15 #include <drivers/generic_delay_timer.h>
16 #include <lib/el3_runtime/context_mgmt.h>
17 #include <lib/mmio.h>
18 #include <lib/utils_def.h>
19 #include <lib/xlat_tables/xlat_tables.h>
20 #include <plat/common/common_def.h>
21 #include <plat/common/platform.h>
22
23 #include <mcucfg.h>
24 #include <mt_cpuxgpt.h>
25 #include <mtk_plat_common.h>
26 #include <mtk_sip_svc.h>
27 #include <plat_private.h>
28
29 /*******************************************************************************
30 * Declarations of linker defined symbols which will help us find the layout
31 * of trusted SRAM
32 ******************************************************************************/
33 /*
34 * The next 2 constants identify the extents of the code & RO data region.
35 * These addresses are used by the MMU setup code and therefore they must be
36 * page-aligned. It is the responsibility of the linker script to ensure that
37 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
38 */
39 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE);
40 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT);
41
42 /*
43 * Placeholder variables for copying the arguments that have been passed to
44 * BL3-1 from BL2.
45 */
46 static entry_point_info_t bl32_image_ep_info;
47 static entry_point_info_t bl33_image_ep_info;
48
49 static const int cci_map[] = {
50 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
51 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
52 };
53
54 static uint32_t cci_map_length = ARRAY_SIZE(cci_map);
55
56 /* Table of regions to map using the MMU. */
57 static const mmap_region_t plat_mmap[] = {
58 /* for TF text, RO, RW */
59 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
60 MT_DEVICE | MT_RW | MT_SECURE),
61 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
62 MT_DEVICE | MT_RW | MT_SECURE),
63 MAP_REGION_FLAT(RAM_CONSOLE_BASE & ~(PAGE_SIZE_MASK), RAM_CONSOLE_SIZE,
64 MT_DEVICE | MT_RW | MT_NS),
65 { 0 }
66
67 };
68
69 /*******************************************************************************
70 * Macro generating the code for the function setting up the pagetables as per
71 * the platform memory map & initialize the mmu, for the given exception level
72 ******************************************************************************/
73 #define DEFINE_CONFIGURE_MMU_EL(_el) \
74 void plat_configure_mmu_el ## _el(unsigned long total_base, \
75 unsigned long total_size, \
76 unsigned long ro_start, \
77 unsigned long ro_limit, \
78 unsigned long coh_start, \
79 unsigned long coh_limit) \
80 { \
81 mmap_add_region(total_base, total_base, \
82 total_size, \
83 MT_MEMORY | MT_RW | MT_SECURE); \
84 mmap_add_region(ro_start, ro_start, \
85 ro_limit - ro_start, \
86 MT_MEMORY | MT_RO | MT_SECURE); \
87 mmap_add_region(coh_start, coh_start, \
88 coh_limit - coh_start, \
89 MT_DEVICE | MT_RW | MT_SECURE); \
90 mmap_add(plat_mmap); \
91 init_xlat_tables(); \
92 \
93 enable_mmu_el ## _el(0); \
94 }
95
96 /* Define EL3 variants of the function initialising the MMU */
97 DEFINE_CONFIGURE_MMU_EL(3)
98
plat_get_syscnt_freq2(void)99 unsigned int plat_get_syscnt_freq2(void)
100 {
101 return SYS_COUNTER_FREQ_IN_TICKS;
102 }
103
plat_cci_init(void)104 void plat_cci_init(void)
105 {
106 /* Initialize CCI driver */
107 cci_init(PLAT_MT_CCI_BASE, cci_map, cci_map_length);
108 }
109
plat_cci_enable(void)110 void plat_cci_enable(void)
111 {
112 /*
113 * Enable CCI coherency for this cluster.
114 * No need for locks as no other cpu is active at the moment.
115 */
116 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
117 }
118
plat_cci_disable(void)119 void plat_cci_disable(void)
120 {
121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
122 }
123
124
platform_setup_cpu(void)125 static void platform_setup_cpu(void)
126 {
127 /* setup big cores */
128 mmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res,
129 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
130 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
131 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
132 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
133 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
134 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS);
135 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div,
136 MP1_SW_CG_GEN);
137 mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl,
138 MP1_L2RSTDISABLE);
139
140 /* set big cores arm64 boot mode */
141 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg,
142 MP1_CPUCFG_64BIT);
143
144 /* set LITTLE cores arm64 boot mode */
145 mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw,
146 MP0_CPUCFG_64BIT);
147 }
148
149 /*******************************************************************************
150 * Return a pointer to the 'entry_point_info' structure of the next image for
151 * the security state specified. BL33 corresponds to the non-secure image type
152 * while BL32 corresponds to the secure image type. A NULL pointer is returned
153 * if the image does not exist.
154 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)155 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
156 {
157 entry_point_info_t *next_image_info;
158
159 next_image_info = (type == NON_SECURE) ?
160 &bl33_image_ep_info : &bl32_image_ep_info;
161
162 /* None of the images on this platform can have 0x0 as the entrypoint */
163 if (next_image_info->pc)
164 return next_image_info;
165 else
166 return NULL;
167 }
168
169 /*******************************************************************************
170 * Perform any BL3-1 early platform setup. Here is an opportunity to copy
171 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
172 * are lost (potentially). This needs to be done before the MMU is initialized
173 * so that the memory layout can be used while creating page tables.
174 * BL2 has flushed this information to memory, so we are guaranteed to pick up
175 * good data.
176 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)177 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
178 u_register_t arg2, u_register_t arg3)
179 {
180 struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0;
181 struct atf_arg_t *teearg;
182 unsigned long long normal_base;
183 unsigned long long atf_base;
184
185 assert(pmtk_bl_param != NULL);
186 /*
187 * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits
188 * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit
189 * to 64 bit state. So we need to clear high 32bit,
190 * which may be random value.
191 */
192 pmtk_bl_param =
193 (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff);
194
195 teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr;
196
197 console_init(teearg->atf_log_port, UART_CLOCK, UART_BAUDRATE);
198 memcpy((void *)>eearg, (void *)teearg, sizeof(struct atf_arg_t));
199
200 normal_base = 0;
201 /* in ATF boot time, timer for cntpct_el0 is not initialized
202 * so it will not count now.
203 */
204 atf_base = read_cntpct_el0();
205 sched_clock_init(normal_base, atf_base);
206
207 VERBOSE("bl31_setup\n");
208
209 /* Populate entry point information for BL3-2 and BL3-3 */
210 SET_PARAM_HEAD(&bl32_image_ep_info,
211 PARAM_EP,
212 VERSION_1,
213 0);
214 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
215 bl32_image_ep_info.pc = BL32_BASE;
216
217 SET_PARAM_HEAD(&bl33_image_ep_info,
218 PARAM_EP,
219 VERSION_1,
220 0);
221 /*
222 * Tell BL3-1 where the non-trusted software image
223 * is located and the entry state information
224 */
225 /* BL33_START_ADDRESS */
226 bl33_image_ep_info.pc = pmtk_bl_param->bl33_start_addr;
227 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry();
228 bl33_image_ep_info.args.arg4 = pmtk_bl_param->bootarg_loc;
229 bl33_image_ep_info.args.arg5 = pmtk_bl_param->bootarg_size;
230 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
231 }
232 /*******************************************************************************
233 * Perform any BL3-1 platform setup code
234 ******************************************************************************/
235
bl31_platform_setup(void)236 void bl31_platform_setup(void)
237 {
238 platform_setup_cpu();
239
240 generic_delay_timer_init();
241
242 plat_mt_gic_driver_init();
243 /* Initialize the gic cpu and distributor interfaces */
244 plat_mt_gic_init();
245
246 /* Topologies are best known to the platform. */
247 mt_setup_topology();
248 }
249 /*******************************************************************************
250 * Perform the very early platform specific architectural setup here. At the
251 * moment this is only intializes the mmu in a quick and dirty way.
252 * Init MTK propiartary log buffer control field.
253 ******************************************************************************/
bl31_plat_arch_setup(void)254 void bl31_plat_arch_setup(void)
255 {
256 /* Enable non-secure access to CCI-400 registers */
257 mmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET, 0x1);
258
259 plat_cci_init();
260 plat_cci_enable();
261
262 if (gteearg.atf_log_buf_size != 0) {
263 INFO("mmap atf buffer : 0x%x, 0x%x\n\r",
264 gteearg.atf_log_buf_start,
265 gteearg.atf_log_buf_size);
266
267 mmap_add_region(
268 gteearg.atf_log_buf_start &
269 ~(PAGE_SIZE_2MB_MASK),
270 gteearg.atf_log_buf_start &
271 ~(PAGE_SIZE_2MB_MASK),
272 PAGE_SIZE_2MB,
273 MT_DEVICE | MT_RW | MT_NS);
274
275 INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n",
276 (gteearg.atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)),
277 PAGE_SIZE_2MB);
278 }
279 /*
280 * add TZRAM_BASE to memory map
281 * then set RO and COHERENT to different attribute
282 */
283 plat_configure_mmu_el3(
284 (TZRAM_BASE & ~(PAGE_SIZE_MASK)),
285 (TZRAM_SIZE & ~(PAGE_SIZE_MASK)),
286 (BL31_RO_BASE & ~(PAGE_SIZE_MASK)),
287 BL31_RO_LIMIT,
288 BL_COHERENT_RAM_BASE,
289 BL_COHERENT_RAM_END);
290 /* Initialize for ATF log buffer */
291 if (gteearg.atf_log_buf_size != 0) {
292 gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE;
293 gteearg.atf_aee_debug_buf_start =
294 gteearg.atf_log_buf_start +
295 gteearg.atf_log_buf_size - ATF_AEE_BUFFER_SIZE;
296 INFO("ATF log service is registered (0x%x, aee:0x%x)\n",
297 gteearg.atf_log_buf_start,
298 gteearg.atf_aee_debug_buf_start);
299 } else{
300 gteearg.atf_aee_debug_buf_size = 0;
301 gteearg.atf_aee_debug_buf_start = 0;
302 }
303
304 /* Platform code before bl31_main */
305 /* compatible to the earlier chipset */
306
307 /* Show to ATF log buffer & UART */
308 INFO("BL3-1: %s\n", version_string);
309 INFO("BL3-1: %s\n", build_message);
310
311 }
312 #if 0
313 /* MTK Define */
314 #define ACTLR_CPUECTLR_BIT (1 << 1)
315
316 void enable_ns_access_to_cpuectlr(void)
317 {
318 unsigned int next_actlr;
319
320
321 /* ACTLR_EL1 do not implement CUPECTLR */
322 next_actlr = read_actlr_el2();
323 next_actlr |= ACTLR_CPUECTLR_BIT;
324 write_actlr_el2(next_actlr);
325
326 next_actlr = read_actlr_el3();
327 next_actlr |= ACTLR_CPUECTLR_BIT;
328 write_actlr_el3(next_actlr);
329 }
330 #endif
331 /*******************************************************************************
332 * This function prepare boot argument for 64 bit kernel entry
333 ******************************************************************************/
bl31_plat_get_next_kernel64_ep_info(void)334 static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void)
335 {
336 entry_point_info_t *next_image_info;
337 unsigned int mode;
338
339 mode = 0;
340
341 /* Kernel image is always non-secured */
342 next_image_info = &bl33_image_ep_info;
343
344 /* Figure out what mode we enter the non-secure world in */
345 if (el_implemented(2) != EL_IMPL_NONE) {
346 INFO("Kernel_EL2\n");
347 mode = MODE_EL2;
348 } else{
349 INFO("Kernel_EL1\n");
350 mode = MODE_EL1;
351 }
352
353 INFO("Kernel is 64Bit\n");
354 next_image_info->spsr =
355 SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
356 next_image_info->pc = get_kernel_info_pc();
357 next_image_info->args.arg0 = get_kernel_info_r0();
358 next_image_info->args.arg1 = get_kernel_info_r1();
359
360 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx\n",
361 next_image_info->pc,
362 next_image_info->args.arg0,
363 next_image_info->args.arg1);
364
365
366 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
367
368 /* None of the images on this platform can have 0x0 as the entrypoint */
369 if (next_image_info->pc)
370 return next_image_info;
371 else
372 return NULL;
373 }
374
375 /*******************************************************************************
376 * This function prepare boot argument for 32 bit kernel entry
377 ******************************************************************************/
bl31_plat_get_next_kernel32_ep_info(void)378 static entry_point_info_t *bl31_plat_get_next_kernel32_ep_info(void)
379 {
380 entry_point_info_t *next_image_info;
381 unsigned int mode;
382
383 mode = 0;
384
385 /* Kernel image is always non-secured */
386 next_image_info = &bl33_image_ep_info;
387
388 /* Figure out what mode we enter the non-secure world in */
389 mode = MODE32_hyp;
390 /*
391 * TODO: Consider the possibility of specifying the SPSR in
392 * the FIP ToC and allowing the platform to have a say as
393 * well.
394 */
395
396 INFO("Kernel is 32Bit\n");
397 next_image_info->spsr =
398 SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE,
399 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT));
400 next_image_info->pc = get_kernel_info_pc();
401 next_image_info->args.arg0 = get_kernel_info_r0();
402 next_image_info->args.arg1 = get_kernel_info_r1();
403 next_image_info->args.arg2 = get_kernel_info_r2();
404
405 INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx, r2=0x%lx\n",
406 next_image_info->pc,
407 next_image_info->args.arg0,
408 next_image_info->args.arg1,
409 next_image_info->args.arg2);
410
411
412 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE);
413
414 /* None of the images on this platform can have 0x0 as the entrypoint */
415 if (next_image_info->pc)
416 return next_image_info;
417 else
418 return NULL;
419 }
420
421 /*******************************************************************************
422 * This function prepare boot argument for kernel entrypoint
423 ******************************************************************************/
bl31_prepare_kernel_entry(uint64_t k32_64)424 void bl31_prepare_kernel_entry(uint64_t k32_64)
425 {
426 entry_point_info_t *next_image_info;
427 uint32_t image_type;
428
429 /* Determine which image to execute next */
430 /* image_type = bl31_get_next_image_type(); */
431 image_type = NON_SECURE;
432
433 /* Program EL3 registers to enable entry into the next EL */
434 if (k32_64 == 0)
435 next_image_info = bl31_plat_get_next_kernel32_ep_info();
436 else
437 next_image_info = bl31_plat_get_next_kernel64_ep_info();
438
439 assert(next_image_info);
440 assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
441
442 INFO("BL3-1: Preparing for EL3 exit to %s world, Kernel\n",
443 (image_type == SECURE) ? "secure" : "normal");
444 INFO("BL3-1: Next image address = 0x%llx\n",
445 (unsigned long long) next_image_info->pc);
446 INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
447 cm_init_my_context(next_image_info);
448 cm_prepare_el3_exit(image_type);
449 }
450