1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x10000000 19 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 20 #define MTK_DEV_RNG2_SIZE 0x600000 21 #define MTK_MCDI_SRAM_BASE 0x11B000 22 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 23 24 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 25 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 26 #define SPM_BASE (IO_PHYS + 0x00006000) 27 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 28 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 29 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 30 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 31 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 32 #define VDOSYS0_BASE (IO_PHYS + 0x0C01A000) 33 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 34 35 /******************************************************************************* 36 * DP/eDP related constants 37 ******************************************************************************/ 38 #define eDP_SEC_BASE (IO_PHYS + 0x0C504000) 39 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 40 #define eDP_SEC_SIZE 0x1000 41 #define DP_SEC_SIZE 0x1000 42 43 /******************************************************************************* 44 * GPIO related constants 45 ******************************************************************************/ 46 #define GPIO_BASE (IO_PHYS + 0x00005000) 47 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 48 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 49 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 50 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 51 #define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000) 52 #define IOCFG_TL_BASE (IO_PHYS + 0x01F40000) 53 54 /******************************************************************************* 55 * UART related constants 56 ******************************************************************************/ 57 #define UART0_BASE (IO_PHYS + 0x01001100) 58 #define UART1_BASE (IO_PHYS + 0x01001200) 59 60 #define UART_BAUDRATE 115200 61 62 /******************************************************************************* 63 * PMIC related constants 64 ******************************************************************************/ 65 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 66 67 /******************************************************************************* 68 * System counter frequency related constants 69 ******************************************************************************/ 70 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 71 #define SYS_COUNTER_FREQ_IN_MHZ 13 72 73 /******************************************************************************* 74 * GIC-600 & interrupt handling related constants 75 ******************************************************************************/ 76 /* Base MTK_platform compatible GIC memory map */ 77 #define BASE_GICD_BASE MT_GIC_BASE 78 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 79 80 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 81 #define CIRQ_REG_NUM 23 82 #define CIRQ_IRQ_NUM 730 83 #define CIRQ_SPI_START 96 84 #define MD_WDT_IRQ_BIT_ID 141 85 /******************************************************************************* 86 * Platform binary types for linking 87 ******************************************************************************/ 88 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 89 #define PLATFORM_LINKER_ARCH aarch64 90 91 /******************************************************************************* 92 * Generic platform constants 93 ******************************************************************************/ 94 #define PLATFORM_STACK_SIZE 0x800 95 96 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 97 98 #define PLAT_MAX_PWR_LVL U(3) 99 #define PLAT_MAX_RET_STATE U(1) 100 #define PLAT_MAX_OFF_STATE U(9) 101 102 #define PLATFORM_SYSTEM_COUNT U(1) 103 #define PLATFORM_MCUSYS_COUNT U(1) 104 #define PLATFORM_CLUSTER_COUNT U(1) 105 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 106 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 107 108 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 109 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 110 111 #define SOC_CHIP_ID U(0x8195) 112 113 /******************************************************************************* 114 * Platform memory map related constants 115 ******************************************************************************/ 116 #define TZRAM_BASE 0x54600000 117 #define TZRAM_SIZE 0x00030000 118 119 /******************************************************************************* 120 * BL31 specific defines. 121 ******************************************************************************/ 122 /* 123 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 124 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 125 * little space for growth. 126 */ 127 #define BL31_BASE (TZRAM_BASE + 0x1000) 128 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 129 130 /******************************************************************************* 131 * Platform specific page table and MMU setup constants 132 ******************************************************************************/ 133 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 134 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 135 #define MAX_XLAT_TABLES 16 136 #define MAX_MMAP_REGIONS 16 137 138 /******************************************************************************* 139 * Declarations and constants to access the mailboxes safely. Each mailbox is 140 * aligned on the biggest cache line size in the platform. This is known only 141 * to the platform as it might have a combination of integrated and external 142 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 143 * line at any cache level. They could belong to different cpus/clusters & 144 * get written while being protected by different locks causing corruption of 145 * a valid mailbox address. 146 ******************************************************************************/ 147 #define CACHE_WRITEBACK_SHIFT 6 148 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 149 #endif /* PLATFORM_DEF_H */ 150