1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /* common headers */
8 #include <assert.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/gpio.h>
13 #include <lib/psci/psci.h>
14
15 /* platform specific headers */
16 #include <mt_gic_v3.h>
17 #include <mtk_ptp3_common.h>
18 #include <mtspmc.h>
19 #include <plat/common/platform.h>
20 #include <plat_mtk_lpm.h>
21 #include <plat_params.h>
22 #include <plat_pm.h>
23 #include <pmic.h>
24 #include <rtc.h>
25
26 /*
27 * Cluster state request:
28 * [0] : The CPU requires cluster power down
29 * [1] : The CPU requires cluster power on
30 */
31 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
32 #define coordinate_cluster_pwron() coordinate_cluster(1)
33 #define coordinate_cluster_pwroff() coordinate_cluster(0)
34
35 /* platform secure entry point */
36 static uintptr_t secure_entrypoint;
37 /* per-CPU power state */
38 static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
39
40 /* platform CPU power domain - ops */
41 static const struct mt_lpm_tz *plat_mt_pm;
42
43 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
44 int ret = -1; \
45 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
46 ret = plat_mt_pm->_name(_cpu, _state); \
47 } \
48 ret; })
49
50 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
51 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
52 (void) plat_mt_pm->_name(_cpu, _state); \
53 } \
54 })
55
56 /*
57 * Common MTK_platform operations to power on/off a
58 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
59 */
60
plat_cpu_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)61 static void plat_cpu_pwrdwn_common(unsigned int cpu,
62 const psci_power_state_t *state, unsigned int req_pstate)
63 {
64 assert(cpu == plat_my_core_pos());
65
66 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
67
68 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
69 (req_pstate == 0U)) { /* hotplug off */
70 coordinate_cluster_pwroff();
71 }
72
73 /* Prevent interrupts from spuriously waking up this CPU */
74 mt_gic_rdistif_save();
75 gicv3_cpuif_disable(cpu);
76 gicv3_rdistif_off(cpu);
77 }
78
plat_cpu_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)79 static void plat_cpu_pwron_common(unsigned int cpu,
80 const psci_power_state_t *state, unsigned int req_pstate)
81 {
82 assert(cpu == plat_my_core_pos());
83
84 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
85
86 coordinate_cluster_pwron();
87
88 /* PTP3 config */
89 ptp3_core_init(cpu);
90
91 /*
92 * If mcusys does power down before then restore
93 * all CPUs' GIC Redistributors
94 */
95 if (IS_MCUSYS_OFF_STATE(state)) {
96 mt_gic_rdistif_restore_all();
97 } else {
98 gicv3_rdistif_on(cpu);
99 gicv3_cpuif_enable(cpu);
100 mt_gic_rdistif_init();
101 mt_gic_rdistif_restore();
102 }
103 }
104
105 /*
106 * Common MTK_platform operations to power on/off a
107 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
108 */
109
plat_cluster_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)110 static void plat_cluster_pwrdwn_common(unsigned int cpu,
111 const psci_power_state_t *state, unsigned int req_pstate)
112 {
113 assert(cpu == plat_my_core_pos());
114
115 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
116 coordinate_cluster_pwron();
117
118 /* TODO: return on fail.
119 * Add a 'return' here before adding any code following
120 * the if-block.
121 */
122 }
123 }
124
plat_cluster_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)125 static void plat_cluster_pwron_common(unsigned int cpu,
126 const psci_power_state_t *state, unsigned int req_pstate)
127 {
128 assert(cpu == plat_my_core_pos());
129
130 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
131 /* TODO: return on fail.
132 * Add a 'return' here before adding any code following
133 * the if-block.
134 */
135 }
136 }
137
138 /*
139 * Common MTK_platform operations to power on/off a
140 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
141 */
142
plat_mcusys_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)143 static void plat_mcusys_pwrdwn_common(unsigned int cpu,
144 const psci_power_state_t *state, unsigned int req_pstate)
145 {
146 assert(cpu == plat_my_core_pos());
147
148 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
149 return; /* return on fail */
150 }
151
152 mt_gic_distif_save();
153 gic_sgi_save_all();
154 }
155
plat_mcusys_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)156 static void plat_mcusys_pwron_common(unsigned int cpu,
157 const psci_power_state_t *state, unsigned int req_pstate)
158 {
159 assert(cpu == plat_my_core_pos());
160
161 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
162 return; /* return on fail */
163 }
164
165 mt_gic_init();
166 mt_gic_distif_restore();
167 gic_sgi_restore_all();
168
169 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
170 }
171
172 /*
173 * plat_psci_ops implementation
174 */
175
plat_cpu_standby(plat_local_state_t cpu_state)176 static void plat_cpu_standby(plat_local_state_t cpu_state)
177 {
178 uint64_t scr;
179
180 scr = read_scr_el3();
181 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
182
183 isb();
184 dsb();
185 wfi();
186
187 write_scr_el3(scr);
188 }
189
plat_power_domain_on(u_register_t mpidr)190 static int plat_power_domain_on(u_register_t mpidr)
191 {
192 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
193 unsigned int cluster = 0U;
194
195 if (cpu >= PLATFORM_CORE_COUNT) {
196 return PSCI_E_INVALID_PARAMS;
197 }
198
199 if (!spm_get_cluster_powerstate(cluster)) {
200 spm_poweron_cluster(cluster);
201 }
202
203 /* init CPU reset arch as AARCH64 */
204 mcucfg_init_archstate(cluster, cpu, true);
205 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
206 spm_poweron_cpu(cluster, cpu);
207
208 return PSCI_E_SUCCESS;
209 }
210
plat_power_domain_on_finish(const psci_power_state_t * state)211 static void plat_power_domain_on_finish(const psci_power_state_t *state)
212 {
213 unsigned long mpidr = read_mpidr_el1();
214 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
215
216 assert(cpu < PLATFORM_CORE_COUNT);
217
218 /* Allow IRQs to wakeup this core in IDLE flow */
219 mcucfg_enable_gic_wakeup(0U, cpu);
220
221 if (IS_CLUSTER_OFF_STATE(state)) {
222 plat_cluster_pwron_common(cpu, state, 0U);
223 }
224
225 plat_cpu_pwron_common(cpu, state, 0U);
226 }
227
plat_power_domain_off(const psci_power_state_t * state)228 static void plat_power_domain_off(const psci_power_state_t *state)
229 {
230 unsigned long mpidr = read_mpidr_el1();
231 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
232
233 assert(cpu < PLATFORM_CORE_COUNT);
234
235 plat_cpu_pwrdwn_common(cpu, state, 0U);
236 spm_poweroff_cpu(0U, cpu);
237
238 /* prevent unintended IRQs from waking up the hot-unplugged core */
239 mcucfg_disable_gic_wakeup(0U, cpu);
240
241 if (IS_CLUSTER_OFF_STATE(state)) {
242 plat_cluster_pwrdwn_common(cpu, state, 0U);
243 }
244 }
245
plat_power_domain_suspend(const psci_power_state_t * state)246 static void plat_power_domain_suspend(const psci_power_state_t *state)
247 {
248 unsigned int cpu = plat_my_core_pos();
249
250 assert(cpu < PLATFORM_CORE_COUNT);
251
252 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
253
254 /* Perform the common CPU specific operations */
255 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
256
257 if (IS_CLUSTER_OFF_STATE(state)) {
258 /* Perform the common cluster specific operations */
259 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
260 }
261
262 if (IS_MCUSYS_OFF_STATE(state)) {
263 /* Perform the common mcusys specific operations */
264 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
265 }
266 }
267
plat_power_domain_suspend_finish(const psci_power_state_t * state)268 static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
269 {
270 unsigned int cpu = plat_my_core_pos();
271
272 assert(cpu < PLATFORM_CORE_COUNT);
273
274 if (IS_MCUSYS_OFF_STATE(state)) {
275 /* Perform the common mcusys specific operations */
276 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
277 }
278
279 if (IS_CLUSTER_OFF_STATE(state)) {
280 /* Perform the common cluster specific operations */
281 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
282 }
283
284 /* Perform the common CPU specific operations */
285 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
286
287 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
288 }
289
plat_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)290 static int plat_validate_power_state(unsigned int power_state,
291 psci_power_state_t *req_state)
292 {
293 unsigned int pstate = psci_get_pstate_type(power_state);
294 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
295 unsigned int cpu = plat_my_core_pos();
296
297 if (aff_lvl > PLAT_MAX_PWR_LVL) {
298 return PSCI_E_INVALID_PARAMS;
299 }
300
301 if (pstate == PSTATE_TYPE_STANDBY) {
302 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
303 } else {
304 unsigned int i;
305 unsigned int pstate_id = psci_get_pstate_id(power_state);
306 plat_local_state_t s = MTK_LOCAL_STATE_OFF;
307
308 /* Use pstate_id to be power domain state */
309 if (pstate_id > s) {
310 s = (plat_local_state_t)pstate_id;
311 }
312
313 for (i = 0U; i <= aff_lvl; i++) {
314 req_state->pwr_domain_state[i] = s;
315 }
316 }
317
318 plat_power_state[cpu] = power_state;
319 return PSCI_E_SUCCESS;
320 }
321
plat_get_sys_suspend_power_state(psci_power_state_t * req_state)322 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
323 {
324 unsigned int lv;
325 unsigned int cpu = plat_my_core_pos();
326
327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
328 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
329 }
330
331 plat_power_state[cpu] =
332 psci_make_powerstate(
333 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
334 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
335
336 flush_dcache_range((uintptr_t)
337 &plat_power_state[cpu],
338 sizeof(plat_power_state[cpu]));
339 }
340
341 /*******************************************************************************
342 * MTK handlers to shutdown/reboot the system
343 ******************************************************************************/
plat_mtk_system_reset(void)344 static void __dead2 plat_mtk_system_reset(void)
345 {
346 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
347
348 INFO("MTK System Reset\n");
349
350 gpio_set_value(gpio_reset->index, gpio_reset->polarity);
351
352 wfi();
353 ERROR("MTK System Reset: operation not handled.\n");
354 panic();
355 }
356
plat_mtk_system_off(void)357 static void __dead2 plat_mtk_system_off(void)
358 {
359 INFO("MTK System Off\n");
360
361 rtc_power_off_sequence();
362 pmic_power_off();
363
364 wfi();
365 ERROR("MTK System Off: operation not handled.\n");
366 panic();
367 }
368
369 static const plat_psci_ops_t plat_psci_ops = {
370 .system_reset = plat_mtk_system_reset,
371 .system_off = plat_mtk_system_off,
372 .cpu_standby = plat_cpu_standby,
373 .pwr_domain_on = plat_power_domain_on,
374 .pwr_domain_on_finish = plat_power_domain_on_finish,
375 .pwr_domain_off = plat_power_domain_off,
376 .pwr_domain_suspend = plat_power_domain_suspend,
377 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
378 .validate_power_state = plat_validate_power_state,
379 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
380 };
381
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)382 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
383 const plat_psci_ops_t **psci_ops)
384 {
385 *psci_ops = &plat_psci_ops;
386 secure_entrypoint = sec_entrypoint;
387
388 /*
389 * init the warm reset config for boot CPU
390 * reset arch as AARCH64
391 * reset addr as function bl31_warm_entrypoint()
392 */
393 mcucfg_init_archstate(0U, 0U, true);
394 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
395
396 spmc_init();
397 plat_mt_pm = mt_plat_cpu_pm_init();
398
399 return 0;
400 }
401