1 /*
2  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SE_PRIVATE_H
9 #define SE_PRIVATE_H
10 
11 #include <lib/utils_def.h>
12 #include <tegra_def.h>
13 
14 /* SE0 security register */
15 #define SE0_SECURITY				U(0x18)
16 #define SE0_SECURITY_SE_SOFT_SETTING		(((uint32_t)1) << 16U)
17 
18 /* SE0 SHA GSCID register */
19 #define SE0_SHA_GSCID_0				U(0x100)
20 
21 /* SE0 config register */
22 #define SE0_SHA_CONFIG				U(0x104)
23 #define SE0_SHA_TASK_CONFIG			U(0x108)
24 #define SE0_SHA_CONFIG_HW_INIT_HASH		(((uint32_t)1) << 0U)
25 #define SE0_SHA_CONFIG_HW_INIT_HASH_DISABLE	U(0)
26 
27 #define SE0_CONFIG_ENC_ALG_SHIFT		U(12)
28 #define SE0_CONFIG_ENC_ALG_SHA	\
29 		(((uint32_t)3) << SE0_CONFIG_ENC_ALG_SHIFT)
30 #define SE0_CONFIG_DEC_ALG_SHIFT		U(8)
31 #define SE0_CONFIG_DEC_ALG_NOP	\
32 		(((uint32_t)0) << SE0_CONFIG_DEC_ALG_SHIFT)
33 #define SE0_CONFIG_DST_SHIFT			U(2)
34 #define SE0_CONFIG_DST_HASHREG	\
35 		(((uint32_t)1) << SE0_CONFIG_DST_SHIFT)
36 #define SHA256_HASH_SIZE_BYTES			U(256)
37 
38 #define SE0_CONFIG_ENC_MODE_SHIFT		U(24)
39 #define SE0_CONFIG_ENC_MODE_SHA256	\
40 			(((uint32_t)5) << SE0_CONFIG_ENC_MODE_SHIFT)
41 
42 /* SHA input message length */
43 #define SE0_IN_ADDR				U(0x10c)
44 #define SE0_IN_HI_ADDR_HI			U(0x110)
45 #define SE0_IN_HI_ADDR_HI_0_MSB_SHIFT		U(24)
46 
47 /* SHA input message length */
48 #define SE0_SHA_MSG_LENGTH_0			U(0x11c)
49 #define SE0_SHA_MSG_LENGTH_1			U(0x120)
50 #define SE0_SHA_MSG_LENGTH_2			U(0x124)
51 #define SE0_SHA_MSG_LENGTH_3			U(0x128)
52 
53 /* SHA input message left  */
54 #define SE0_SHA_MSG_LEFT_0			U(0x12c)
55 #define SE0_SHA_MSG_LEFT_1			U(0x130)
56 #define SE0_SHA_MSG_LEFT_2			U(0x134)
57 #define SE0_SHA_MSG_LEFT_3			U(0x138)
58 
59 /* SE HASH-RESULT */
60 #define SE0_SHA_HASH_RESULT_0			U(0x13c)
61 
62 /* SE OPERATION */
63 #define SE0_OPERATION_REG_OFFSET		U(0x17c)
64 #define SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT	U(16)
65 #define SE0_UNIT_OPERATION_PKT_LASTBUF_FIELD	\
66 		((uint32_t)0x1 << SE0_UNIT_OPERATION_PKT_LASTBUF_SHIFT)
67 #define SE0_OPERATION_SHIFT			U(0)
68 #define SE0_OP_START	\
69 		(((uint32_t)0x1) << SE0_OPERATION_SHIFT)
70 
71 /* SE Interrupt */
72 #define SE0_SHA_INT_ENABLE			U(0x180)
73 
74 #define SE0_INT_STATUS_REG_OFFSET		U(0x184)
75 #define SE0_INT_OP_DONE_SHIFT			U(4)
76 #define SE0_INT_OP_DONE_CLEAR	\
77 		(((uint32_t)0U) << SE0_INT_OP_DONE_SHIFT)
78 #define SE0_INT_OP_DONE(x)	\
79 		((x) & (((uint32_t)0x1U) << SE0_INT_OP_DONE_SHIFT))
80 
81 /* SE SHA Status */
82 #define SE0_SHA_STATUS_0			U(0x188)
83 #define SE0_SHA_STATUS_IDLE			U(0)
84 
85 /* SE error status */
86 #define SE0_ERR_STATUS_REG_OFFSET		U(0x18c)
87 #define SE0_ERR_STATUS_CLEAR			U(0)
88 
89 /* SE error status */
90 #define SECURE_SCRATCH_TZDRAM_SHA256_HASH_START	SECURE_SCRATCH_RSV68_LO
91 #define SECURE_SCRATCH_TZDRAM_SHA256_HASH_END	SECURE_SCRATCH_RSV71_HI
92 
93 /* SE0_INT_ENABLE_0 */
94 #define SE0_INT_ENABLE				U(0x88)
95 #define  SE0_DISABLE_ALL_INT			U(0x0)
96 
97 /* SE0_INT_STATUS_0 */
98 #define SE0_INT_STATUS				U(0x8C)
99 #define  SE0_CLEAR_ALL_INT_STATUS		U(0x3F)
100 
101 /* SE0_SHA_INT_STATUS_0 */
102 #define SHA_INT_STATUS				U(0x184)
103 #define SHA_SE_OP_DONE				(U(1) << 4)
104 
105 /* SE0_SHA_ERR_STATUS_0 */
106 #define SHA_ERR_STATUS				U(0x18C)
107 
108 /* SE0_AES0_INT_STATUS_0 */
109 #define AES0_INT_STATUS				U(0x2F0)
110 #define  AES0_SE_OP_DONE			(U(1) << 4)
111 
112 /* SE0_AES0_ERR_STATUS_0 */
113 #define AES0_ERR_STATUS				U(0x2F8)
114 
115 /* SE0_AES1_INT_STATUS_0 */
116 #define AES1_INT_STATUS				U(0x4F0)
117 
118 /* SE0_AES1_ERR_STATUS_0 */
119 #define AES1_ERR_STATUS				U(0x4F8)
120 
121 /* SE0_RSA_INT_STATUS_0 */
122 #define RSA_INT_STATUS				U(0x758)
123 
124 /* SE0_RSA_ERR_STATUS_0 */
125 #define RSA_ERR_STATUS				U(0x760)
126 
127 /* SE0_AES0_OPERATION_0 */
128 #define AES0_OPERATION				U(0x238)
129 #define  OP_MASK_BITS				U(0x7)
130 #define  SE_OP_CTX_SAVE				U(0x3)
131 
132 /* SE0_AES0_CTX_SAVE_CONFIG_0 */
133 #define	CTX_SAVE_CONFIG				U(0x2D4)
134 
135 /* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */
136 #define CTX_SAVE_AUTO_STATUS			U(0x300)
137 #define  CTX_SAVE_AUTO_SE_READY			U(0xFF)
138 #define	 CTX_SAVE_AUTO_SE_BUSY			(U(0x1) << 31)
139 
140 /* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */
141 #define CTX_SAVE_AUTO_CTRL			U(0x304)
142 #define	 SE_CTX_SAVE_AUTO_EN			(U(0x1) << 0)
143 #define	 SE_CTX_SAVE_AUTO_LOCK_EN		(U(0x1) << 1)
144 
145 /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */
146 #define CTX_SAVE_AUTO_START_ADDR		U(0x308)
147 
148 /* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */
149 #define CTX_SAVE_AUTO_START_ADDR_HI		U(0x30C)
150 
151 /*******************************************************************************
152  * Inline functions definition
153  ******************************************************************************/
154 
tegra_se_read_32(uint32_t offset)155 static inline uint32_t tegra_se_read_32(uint32_t offset)
156 {
157 	return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
158 }
159 
tegra_se_write_32(uint32_t offset,uint32_t val)160 static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
161 {
162 	mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
163 }
164 
165 #endif /* SE_PRIVATE_H */
166