1# 2# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc. 3# Copyright 2017-2020 NXP Semiconductors 4# 5# SPDX-License-Identifier: BSD-3-Clause 6# 7# 8#------------------------------------------------------------------------------ 9# 10# This file contains the basic architecture definitions that drive the build 11# 12# ----------------------------------------------------------------------------- 13 14CORE_TYPE := a72 15 16CACHE_LINE := 6 17 18# set to GIC400 or GIC500 19GIC := GIC500 20 21# set to CCI400 or CCN504 or CCN508 22INTERCONNECT := CCN508 23 24# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 25CHASSIS := 3_2 26 27# TZC IP Details TZC used is TZC380 or TZC400 28TZC_ID := TZC400 29 30# CONSOLE Details available is NS16550 or PL011 31CONSOLE := PL011 32 33# Select the DDR PHY generation to be used 34PLAT_DDR_PHY := PHY_GEN2 35 36PHYS_SYS := 64 37 38# Area of OCRAM reserved by ROM code 39NXP_ROM_RSVD := 0xa000 40 41# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 42# Input to CST create_hdr_esbc tool 43CSF_HDR_SZ := 0x3000 44 45NXP_SFP_VER := 3_4 46 47# In IMAGE_BL2, compile time flag for handling Cache coherency 48# with CAAM for BL2 running from OCRAM 49SEC_MEM_NON_COHERENT := yes 50 51# Defining the endianness for NXP ESDHC 52NXP_ESDHC_ENDIANNESS := LE 53 54# Defining the endianness for NXP SFP 55NXP_SFP_ENDIANNESS := LE 56 57# Defining the endianness for NXP GPIO 58NXP_GPIO_ENDIANNESS := LE 59 60# Defining the endianness for NXP SNVS 61NXP_SNVS_ENDIANNESS := LE 62 63# Defining the endianness for NXP CCSR GUR register 64NXP_GUR_ENDIANNESS := LE 65 66# Defining the endianness for NXP FSPI register 67NXP_FSPI_ENDIANNESS := LE 68 69# Defining the endianness for NXP SEC 70NXP_SEC_ENDIANNESS := LE 71 72# Defining the endianness for NXP DDR 73NXP_DDR_ENDIANNESS := LE 74 75NXP_DDR_INTLV_256B := 1 76 77# OCRAM MAP for BL2 78# Before BL2 79# 0x18000000 - 0x18009fff -> Used by ROM code 80# 0x1800a000 - 0x1800dfff -> CSF header for BL2 81# (The above area i.e 0x18000000 - 0x1800dfff is available 82# for DDR PHY images scratch pad region during BL2 run time) 83# For FlexSPI boot 84# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 85# For SD boot 86# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 87# 0x18030000 - 0x18040000 -> Reserved for SD buffer 88OCRAM_START_ADDR := 0x18000000 89OCRAM_SIZE := 0x40000 90 91# Location of BL2 on OCRAM 92BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 93# Covert to HEX to be used by create_pbl.mk 94BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 95 96# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD) 97# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE 98BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) ))) 99# Covert to HEX to be used by create_pbl.mk 100BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 101 102# SoC ERRATAS to be enabled 103# 104# Core Errata 105ERRATA_A72_859971 := 1 106 107# SoC Errata 108ERRATA_SOC_A050426 := 1 109 110# enable dynamic memory mapping 111PLAT_XLAT_TABLES_DYNAMIC := 1 112