1# 2# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include plat/renesas/common/common.mk 8 9ifndef LSI 10 $(error "Error: Unknown LSI. Please use LSI=<LSI name> to specify the LSI") 11else 12 ifeq (${LSI},AUTO) 13 RCAR_LSI:=${RCAR_AUTO} 14 else ifeq (${LSI},G2M) 15 RCAR_LSI:=${RZ_G2M} 16 ifndef LSI_CUT 17 # enable compatible function. 18 RCAR_LSI_CUT_COMPAT := 1 19 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 20 else 21 # disable compatible function. 22 ifeq (${LSI_CUT},10) 23 RCAR_LSI_CUT:=0 24 else ifeq (${LSI_CUT},11) 25 RCAR_LSI_CUT:=1 26 else ifeq (${LSI_CUT},13) 27 RCAR_LSI_CUT:=3 28 else ifeq (${LSI_CUT},30) 29 RCAR_LSI_CUT:=20 30 else 31 $(error "Error: ${LSI_CUT} is not supported.") 32 endif 33 $(eval $(call add_define,RCAR_LSI_CUT)) 34 endif 35 else ifeq (${LSI},G2H) 36 RCAR_LSI:=${RZ_G2H} 37 ifndef LSI_CUT 38 # enable compatible function. 39 RCAR_LSI_CUT_COMPAT := 1 40 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 41 else 42 # disable compatible function. 43 ifeq (${LSI_CUT},30) 44 RCAR_LSI_CUT:=20 45 else 46 $(error "Error: ${LSI_CUT} is not supported.") 47 endif 48 $(eval $(call add_define,RCAR_LSI_CUT)) 49 endif 50 else ifeq (${LSI},G2N) 51 RCAR_LSI:=${RZ_G2N} 52 ifndef LSI_CUT 53 # enable compatible function. 54 RCAR_LSI_CUT_COMPAT := 1 55 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 56 else 57 # disable compatible function. 58 ifeq (${LSI_CUT},10) 59 RCAR_LSI_CUT:=0 60 else ifeq (${LSI_CUT},11) 61 RCAR_LSI_CUT:=1 62 else 63 $(error "Error: ${LSI_CUT} is not supported.") 64 endif 65 $(eval $(call add_define,RCAR_LSI_CUT)) 66 endif 67 else ifeq (${LSI},G2E) 68 RCAR_LSI:=${RZ_G2E} 69 ifndef LSI_CUT 70 # enable compatible function. 71 RCAR_LSI_CUT_COMPAT := 1 72 $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) 73 else 74 # disable compatible function. 75 ifeq (${LSI_CUT},10) 76 RCAR_LSI_CUT:=0 77 else ifeq (${LSI_CUT},11) 78 RCAR_LSI_CUT:=1 79 else 80 $(error "Error: ${LSI_CUT} is not supported.") 81 endif 82 $(eval $(call add_define,RCAR_LSI_CUT)) 83 endif 84 else 85 $(error "Error: ${LSI} is not supported.") 86 endif 87 $(eval $(call add_define,RCAR_LSI)) 88endif 89 90# Process RZG_LCS_STATE_DETECTION_ENABLE flag 91# Enable to get LCS state information 92ifndef RZG_LCS_STATE_DETECTION_ENABLE 93RZG_LCS_STATE_DETECTION_ENABLE := 0 94endif 95$(eval $(call add_define,RZG_LCS_STATE_DETECTION_ENABLE)) 96 97# Process RCAR_SECURE_BOOT flag 98ifndef RCAR_SECURE_BOOT 99RCAR_SECURE_BOOT := 0 100endif 101$(eval $(call add_define,RCAR_SECURE_BOOT)) 102 103# LCS state of RZ/G2 Chip is all CM. 104# However certain chips(RZ/G2M and RZ/G2E) have incorrect factory Fuse settings 105# which results in getting incorrect LCS states 106# if need to enable RCAR_SECURE_BOOT, make sure the chip has proper factory Fuse settings. 107ifeq (${RCAR_SECURE_BOOT},1) 108 ifeq (${RZG_LCS_STATE_DETECTION_ENABLE},0) 109 $(error "Error: Please check the chip has proper factory Fuse settings and set RZG_LCS_STATE_DETECTION_ENABLE to enable.") 110 endif 111endif 112 113# lock RPC HYPERFLASH access by default 114# unlock to repogram the ATF firmware from u-boot 115ifndef RCAR_RPC_HYPERFLASH_LOCKED 116RCAR_RPC_HYPERFLASH_LOCKED := 1 117endif 118$(eval $(call add_define,RCAR_RPC_HYPERFLASH_LOCKED)) 119 120# Process RCAR_QOS_TYPE flag 121ifndef RCAR_QOS_TYPE 122RCAR_QOS_TYPE := 0 123endif 124$(eval $(call add_define,RCAR_QOS_TYPE)) 125 126# Process RCAR_DRAM_SPLIT flag 127ifndef RCAR_DRAM_SPLIT 128RCAR_DRAM_SPLIT := 0 129endif 130$(eval $(call add_define,RCAR_DRAM_SPLIT)) 131 132# Process RCAR_BL33_EXECUTION_EL flag 133ifndef RCAR_BL33_EXECUTION_EL 134RCAR_BL33_EXECUTION_EL := 0 135endif 136$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) 137 138# Process RCAR_AVS_SETTING_ENABLE flag 139ifndef AVS_SETTING_ENABLE 140AVS_SETTING_ENABLE := 0 141endif 142$(eval $(call add_define,AVS_SETTING_ENABLE)) 143 144# Process RCAR_LOSSY_ENABLE flag 145ifndef RCAR_LOSSY_ENABLE 146RCAR_LOSSY_ENABLE := 0 147endif 148$(eval $(call add_define,RCAR_LOSSY_ENABLE)) 149 150# Process LIFEC_DBSC_PROTECT_ENABLE flag 151ifndef LIFEC_DBSC_PROTECT_ENABLE 152LIFEC_DBSC_PROTECT_ENABLE := 1 153endif 154$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE)) 155 156# Process RCAR_GEN3_ULCB flag 157ifndef RCAR_GEN3_ULCB 158RCAR_GEN3_ULCB := 0 159endif 160 161# Process RCAR_REF_INT flag 162ifndef RCAR_REF_INT 163RCAR_REF_INT :=0 164endif 165$(eval $(call add_define,RCAR_REF_INT)) 166 167# Process RCAR_REWT_TRAINING flag 168ifndef RCAR_REWT_TRAINING 169RCAR_REWT_TRAINING := 1 170endif 171$(eval $(call add_define,RCAR_REWT_TRAINING)) 172 173# Process RCAR_SYSTEM_SUSPEND flag 174ifndef RCAR_SYSTEM_SUSPEND 175RCAR_SYSTEM_SUSPEND := 0 176endif 177$(eval $(call add_define,RCAR_SYSTEM_SUSPEND)) 178 179# Process RCAR_DRAM_LPDDR4_MEMCONF flag 180ifndef RCAR_DRAM_LPDDR4_MEMCONF 181RCAR_DRAM_LPDDR4_MEMCONF :=1 182endif 183$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) 184 185# Process RCAR_DRAM_DDR3L_MEMCONF flag 186ifndef RCAR_DRAM_DDR3L_MEMCONF 187RCAR_DRAM_DDR3L_MEMCONF :=1 188endif 189$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMCONF)) 190 191# Process RCAR_DRAM_DDR3L_MEMDUAL flag 192ifndef RCAR_DRAM_DDR3L_MEMDUAL 193RCAR_DRAM_DDR3L_MEMDUAL :=1 194endif 195$(eval $(call add_define,RCAR_DRAM_DDR3L_MEMDUAL)) 196 197# Process RCAR_BL33_ARG0 flag 198ifdef RCAR_BL33_ARG0 199$(eval $(call add_define,RCAR_BL33_ARG0)) 200endif 201 202#Process RCAR_BL2_DCACHE flag 203ifndef RCAR_BL2_DCACHE 204RCAR_BL2_DCACHE := 0 205endif 206$(eval $(call add_define,RCAR_BL2_DCACHE)) 207 208# Process RCAR_DRAM_CHANNEL flag 209ifndef RCAR_DRAM_CHANNEL 210RCAR_DRAM_CHANNEL :=15 211endif 212$(eval $(call add_define,RCAR_DRAM_CHANNEL)) 213 214#Process RCAR_SYSTEM_RESET_KEEPON_DDR flag 215ifndef RCAR_SYSTEM_RESET_KEEPON_DDR 216RCAR_SYSTEM_RESET_KEEPON_DDR := 0 217endif 218$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR)) 219 220RZG_SOC :=1 221$(eval $(call add_define,RZG_SOC)) 222 223include drivers/renesas/common/ddr/ddr.mk 224include drivers/renesas/rzg/qos/qos.mk 225include drivers/renesas/rzg/pfc/pfc.mk 226include lib/libfdt/libfdt.mk 227 228PLAT_INCLUDES += -Idrivers/renesas/common/ddr \ 229 -Idrivers/renesas/rzg/qos \ 230 -Idrivers/renesas/rzg/board \ 231 -Idrivers/renesas/common \ 232 -Idrivers/renesas/common/iic_dvfs \ 233 -Idrivers/renesas/common/avs \ 234 -Idrivers/renesas/common/delay \ 235 -Idrivers/renesas/common/rom \ 236 -Idrivers/renesas/common/scif \ 237 -Idrivers/renesas/common/emmc \ 238 -Idrivers/renesas/common/pwrc \ 239 -Idrivers/renesas/common/io 240 241BL2_SOURCES += plat/renesas/rzg/bl2_plat_setup.c \ 242 drivers/renesas/rzg/board/board.c 243 244# build the layout images for the bootrom and the necessary srecords 245rzg: rzg_layout_create rzg_srecord 246distclean realclean clean: clean_layout_tool clean_srecord 247 248# layout images 249LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create 250 251clean_layout_tool: 252 @echo "clean layout tool" 253 ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean 254 255.PHONY: rzg_layout_create 256rzg_layout_create: 257 @echo "generating layout srecs" 258 ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH} 259 260# srecords 261SREC_PATH = ${BUILD_PLAT} 262BL2_ELF_SRC = ${SREC_PATH}/bl2/bl2.elf 263BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf 264 265clean_srecord: 266 @echo "clean bl2 and bl31 srecs" 267 rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec 268 269.PHONY: rzg_srecord 270rzg_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC) 271 @echo "generating srec: ${SREC_PATH}/bl2.srec" 272 $(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec 273 @echo "generating srec: ${SREC_PATH}/bl31.srec" 274 $(Q)$(OC) -O srec --srec-forceS3 ${BL31_ELF_SRC} ${SREC_PATH}/bl31.srec 275