1 /*
2  * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOC_H
8 #define SOC_H
9 
10 enum plls_id {
11 	ABPLL_ID = 0,
12 	ALPLL_ID,
13 	DPLL_ID,
14 	CPLL_ID,
15 	GPLL_ID,
16 	NPLL_ID,
17 	END_PLL_ID,
18 };
19 
20 /*****************************************************************************
21  * secure timer
22  *****************************************************************************/
23 #define TIMER_LOADE_COUNT0	0x00
24 #define TIMER_LOADE_COUNT1	0x04
25 #define TIMER_CURRENT_VALUE0	0x08
26 #define TIMER_CURRENT_VALUE1	0x0C
27 #define TIMER_CONTROL_REG	0x10
28 #define TIMER_INTSTATUS		0x18
29 
30 #define TIMER_EN		0x1
31 
32 #define STIMER1_BASE		(STIME_BASE + 0x20)
33 
34 #define CYCL_24M_CNT_US(us)	(24 * us)
35 #define CYCL_24M_CNT_MS(ms)	(ms * CYCL_24M_CNT_US(1000))
36 
37 /*****************************************************************************
38  * sgrf reg, offset
39  *****************************************************************************/
40 #define SGRF_SOC_CON(n)		(0x0 + (n) * 4)
41 #define SGRF_BUSDMAC_CON(n)	(0x100 + (n) * 4)
42 
43 #define SGRF_SOC_CON_NS		0xffff0000
44 
45 /*****************************************************************************
46  * con6[2]pmusram is security.
47  * con6[6]stimer is security.
48  *****************************************************************************/
49 #define PMUSRAM_S_SHIFT		2
50 #define PMUSRAM_S		1
51 #define STIMER_S_SHIFT		6
52 #define STIMER_S		1
53 #define SGRF_SOC_CON7_BITS	((0xffffu << 16) | \
54 				 (PMUSRAM_S << PMUSRAM_S_SHIFT) | \
55 				 (STIMER_S << STIMER_S_SHIFT))
56 
57 #define SGRF_BUSDMAC_CON0_NS	0xfffcfff8
58 #define SGRF_BUSDMAC_CON1_NS	0xffff0fff
59 
60 /*
61  * sgrf_soc_con1~2, mask and offset
62  */
63 #define CPU_BOOT_ADDR_WMASK	0xffff0000
64 #define CPU_BOOT_ADDR_ALIGN	16
65 
66 /*****************************************************************************
67  * cru reg, offset
68  *****************************************************************************/
69 #define CRU_SOFTRST_CON		0x300
70 #define CRU_SOFTRSTS_CON(n)	(CRU_SOFTRST_CON + ((n) * 4))
71 #define CRU_SOFTRSTS_CON_CNT	15
72 
73 #define SOFTRST_DMA1		0x40004
74 #define SOFTRST_DMA2		0x10001
75 
76 #define RST_DMA1_MSK		0x4
77 #define RST_DMA2_MSK		0x0
78 
79 #define CRU_CLKSEL_CON		0x100
80 #define CRU_CLKSELS_CON(i)	(CRU_CLKSEL_CON + ((i) * 4))
81 #define CRU_CLKSEL_CON_CNT	56
82 
83 #define CRU_CLKGATE_CON		0x200
84 #define CRU_CLKGATES_CON(i)	(CRU_CLKGATE_CON + ((i) * 4))
85 #define CRU_CLKGATES_CON_CNT	25
86 
87 #define CRU_GLB_SRST_FST	0x280
88 #define CRU_GLB_SRST_SND	0x284
89 #define CRU_GLB_RST_CON		0x388
90 
91 #define CRU_CONS_GATEID(i)	(16 * (i))
92 #define GATE_ID(reg, bit)	((reg * 16) + bit)
93 
94 #define PMU_RST_BY_SECOND_SFT	(BIT(1) << 2)
95 #define PMU_RST_NOT_BY_SFT	(BIT(1) << 2)
96 
97 /***************************************************************************
98  * pll
99  ***************************************************************************/
100 #define PLL_PWR_DN_MSK		(0x1 << 1)
101 #define PLL_PWR_DN		REG_WMSK_BITS(1, 1, 0x1)
102 #define PLL_PWR_ON		REG_WMSK_BITS(0, 1, 0x1)
103 #define PLL_RESET		REG_WMSK_BITS(1, 5, 0x1)
104 #define PLL_RESET_RESUME	REG_WMSK_BITS(0, 5, 0x1)
105 #define PLL_BYPASS_MSK		(0x1 << 0)
106 #define PLL_BYPASS_W_MSK	(PLL_BYPASS_MSK << 16)
107 #define PLL_BYPASS		REG_WMSK_BITS(1, 0, 0x1)
108 #define PLL_NO_BYPASS		REG_WMSK_BITS(0, 0, 0x1)
109 #define PLL_MODE_SHIFT		8
110 #define PLL_MODE_MSK		0x3
111 #define PLLS_MODE_WMASK		(PLL_MODE_MSK << (16 + PLL_MODE_SHIFT))
112 #define PLL_SLOW		0x0
113 #define PLL_NORM		0x1
114 #define PLL_DEEP		0x2
115 #define PLL_SLOW_BITS		REG_WMSK_BITS(PLL_SLOW, 8, 0x3)
116 #define PLL_NORM_BITS		REG_WMSK_BITS(PLL_NORM, 8, 0x3)
117 #define PLL_DEEP_BITS		REG_WMSK_BITS(PLL_DEEP, 8, 0x3)
118 
119 #define PLL_CONS(id, i)		((id) * 0x10 + ((i) * 4))
120 
121 #define REG_W_MSK(bits_shift, msk) \
122 		((msk) << ((bits_shift) + 16))
123 #define REG_VAL_CLRBITS(val, bits_shift, msk) \
124 		(val & (~(msk << bits_shift)))
125 #define REG_SET_BITS(bits, bits_shift, msk) \
126 		(((bits) & (msk)) << (bits_shift))
127 #define REG_WMSK_BITS(bits, bits_shift, msk) \
128 		(REG_W_MSK(bits_shift, msk) | \
129 		REG_SET_BITS(bits, bits_shift, msk))
130 
131 #define regs_updata_bit_set(addr, shift) \
132 		regs_updata_bits((addr), 0x1, 0x1, (shift))
133 #define regs_updata_bit_clr(addr, shift) \
134 		regs_updata_bits((addr), 0x0, 0x1, (shift))
135 
136 void regs_updata_bits(uintptr_t addr, uint32_t val,
137 		      uint32_t mask, uint32_t shift);
138 void soc_sleep_config(void);
139 void pm_plls_resume(void);
140 
141 #endif /* SOC_H */
142