1/*
2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SYNQUACER_PLAT_LD_S__
8#define SYNQUACER_PLAT_LD_S__
9
10#include <lib/xlat_tables/xlat_tables_defs.h>
11
12#define SPM_SHIM_EXCEPTIONS_VMA		SP_DRAM
13
14MEMORY {
15	SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE
16}
17
18SECTIONS
19{
20	/*
21	 * Put the page tables in secure DRAM so that the PTW can make cacheable
22	 * accesses, as the core SPM code expects. (The SRAM on SynQuacer does
23	 * not support inner shareable WBWA mappings so it is mapped normal
24	 * non-cacheable)
25	 */
26	sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
27		*(sp_xlat_table)
28	} >SP_DRAM
29}
30
31#endif /* SYNQUACER_PLAT_LD_S__ */
32