1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv3.h>
13 #include <plat/common/platform.h>
14
15 #include "sq_common.h"
16
17 static uintptr_t sq_rdistif_base_addrs[PLATFORM_CORE_COUNT];
18
19 static const interrupt_prop_t sq_interrupt_props[] = {
20 /* G0 interrupts */
21
22 /* SGI0 */
23 INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
24 GIC_INTR_CFG_EDGE),
25 /* SGI6 */
26 INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
27 GIC_INTR_CFG_EDGE),
28
29 /* G1S interrupts */
30
31 /* Timer */
32 INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
33 GIC_INTR_CFG_LEVEL),
34 /* SGI1 */
35 INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
36 GIC_INTR_CFG_EDGE),
37 /* SGI2 */
38 INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
39 GIC_INTR_CFG_EDGE),
40 /* SGI3 */
41 INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
42 GIC_INTR_CFG_EDGE),
43 /* SGI4 */
44 INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
45 GIC_INTR_CFG_EDGE),
46 /* SGI5 */
47 INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
48 GIC_INTR_CFG_EDGE),
49 /* SGI7 */
50 INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
51 GIC_INTR_CFG_EDGE)
52 };
53
sq_mpidr_to_core_pos(u_register_t mpidr)54 static unsigned int sq_mpidr_to_core_pos(u_register_t mpidr)
55 {
56 return plat_core_pos_by_mpidr(mpidr);
57 }
58
59 static const struct gicv3_driver_data sq_gic_driver_data = {
60 .gicd_base = PLAT_SQ_GICD_BASE,
61 .gicr_base = PLAT_SQ_GICR_BASE,
62 .interrupt_props = sq_interrupt_props,
63 .interrupt_props_num = ARRAY_SIZE(sq_interrupt_props),
64 .rdistif_num = PLATFORM_CORE_COUNT,
65 .rdistif_base_addrs = sq_rdistif_base_addrs,
66 .mpidr_to_core_pos = sq_mpidr_to_core_pos,
67 };
68
sq_gic_driver_init(void)69 void sq_gic_driver_init(void)
70 {
71 gicv3_driver_init(&sq_gic_driver_data);
72 }
73
sq_gic_init(void)74 void sq_gic_init(void)
75 {
76 gicv3_distif_init();
77 gicv3_rdistif_init(plat_my_core_pos());
78 gicv3_cpuif_enable(plat_my_core_pos());
79 }
80
sq_gic_cpuif_enable(void)81 void sq_gic_cpuif_enable(void)
82 {
83 gicv3_cpuif_enable(plat_my_core_pos());
84 }
85
sq_gic_cpuif_disable(void)86 void sq_gic_cpuif_disable(void)
87 {
88 gicv3_cpuif_disable(plat_my_core_pos());
89 }
90
sq_gic_pcpu_init(void)91 void sq_gic_pcpu_init(void)
92 {
93 gicv3_rdistif_init(plat_my_core_pos());
94 }
95