1 /*
2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <common/desc_image_load.h>
16 #include <drivers/delay_timer.h>
17 #include <drivers/generic_delay_timer.h>
18 #include <drivers/st/bsec.h>
19 #include <drivers/st/stm32_console.h>
20 #include <drivers/st/stm32_iwdg.h>
21 #include <drivers/st/stm32mp_pmic.h>
22 #include <drivers/st/stm32mp_reset.h>
23 #include <drivers/st/stm32mp1_clk.h>
24 #include <drivers/st/stm32mp1_pwr.h>
25 #include <drivers/st/stm32mp1_ram.h>
26 #include <lib/mmio.h>
27 #include <lib/optee_utils.h>
28 #include <lib/xlat_tables/xlat_tables_v2.h>
29 #include <plat/common/platform.h>
30
31 #include <stm32mp1_context.h>
32 #include <stm32mp1_dbgmcu.h>
33
34 #define RESET_TIMEOUT_US_1MS 1000U
35
36 static console_t console;
37 static struct stm32mp_auth_ops stm32mp1_auth_ops;
38
print_reset_reason(void)39 static void print_reset_reason(void)
40 {
41 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
42
43 if (rstsr == 0U) {
44 WARN("Reset reason unknown\n");
45 return;
46 }
47
48 INFO("Reset reason (0x%x):\n", rstsr);
49
50 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
51 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
52 INFO("System exits from STANDBY\n");
53 return;
54 }
55
56 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
57 INFO("MPU exits from CSTANDBY\n");
58 return;
59 }
60 }
61
62 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
63 INFO(" Power-on Reset (rst_por)\n");
64 return;
65 }
66
67 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
68 INFO(" Brownout Reset (rst_bor)\n");
69 return;
70 }
71
72 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
73 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
74 INFO(" System reset generated by MCU (MCSYSRST)\n");
75 } else {
76 INFO(" Local reset generated by MCU (MCSYSRST)\n");
77 }
78 return;
79 }
80
81 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
82 INFO(" System reset generated by MPU (MPSYSRST)\n");
83 return;
84 }
85
86 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
87 INFO(" Reset due to a clock failure on HSE\n");
88 return;
89 }
90
91 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
92 INFO(" IWDG1 Reset (rst_iwdg1)\n");
93 return;
94 }
95
96 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
97 INFO(" IWDG2 Reset (rst_iwdg2)\n");
98 return;
99 }
100
101 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
102 INFO(" MPU Processor 0 Reset\n");
103 return;
104 }
105
106 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
107 INFO(" MPU Processor 1 Reset\n");
108 return;
109 }
110
111 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
112 INFO(" Pad Reset from NRST\n");
113 return;
114 }
115
116 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
117 INFO(" Reset due to a failure of VDD_CORE\n");
118 return;
119 }
120
121 ERROR(" Unidentified reset reason\n");
122 }
123
bl2_el3_early_platform_setup(u_register_t arg0,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)124 void bl2_el3_early_platform_setup(u_register_t arg0,
125 u_register_t arg1 __unused,
126 u_register_t arg2 __unused,
127 u_register_t arg3 __unused)
128 {
129 stm32mp_save_boot_ctx_address(arg0);
130 }
131
bl2_platform_setup(void)132 void bl2_platform_setup(void)
133 {
134 int ret;
135
136 if (dt_pmic_status() > 0) {
137 initialize_pmic();
138 }
139
140 ret = stm32mp1_ddr_probe();
141 if (ret < 0) {
142 ERROR("Invalid DDR init: error %d\n", ret);
143 panic();
144 }
145
146 /* Map DDR for binary load, now with cacheable attribute */
147 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
148 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
149 if (ret < 0) {
150 ERROR("DDR mapping: error %d\n", ret);
151 panic();
152 }
153
154 #ifdef AARCH32_SP_OPTEE
155 INFO("BL2 runs OP-TEE setup\n");
156 #else
157 INFO("BL2 runs SP_MIN setup\n");
158 #endif
159 }
160
bl2_el3_plat_arch_setup(void)161 void bl2_el3_plat_arch_setup(void)
162 {
163 int32_t result;
164 struct dt_node_info dt_uart_info;
165 const char *board_model;
166 boot_api_context_t *boot_context =
167 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
168 uint32_t clk_rate;
169 uintptr_t pwr_base;
170 uintptr_t rcc_base;
171
172 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
173 BL_CODE_END - BL_CODE_BASE,
174 MT_CODE | MT_SECURE);
175
176 #ifdef AARCH32_SP_OPTEE
177 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
178 STM32MP_OPTEE_SIZE,
179 MT_MEMORY | MT_RW | MT_SECURE);
180 #endif
181 /* Prevent corruption of preloaded Device Tree */
182 mmap_add_region(DTB_BASE, DTB_BASE,
183 DTB_LIMIT - DTB_BASE,
184 MT_RO_DATA | MT_SECURE);
185
186 configure_mmu();
187
188 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
189 panic();
190 }
191
192 pwr_base = stm32mp_pwr_base();
193 rcc_base = stm32mp_rcc_base();
194
195 /*
196 * Disable the backup domain write protection.
197 * The protection is enable at each reset by hardware
198 * and must be disabled by software.
199 */
200 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
201
202 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
203 ;
204 }
205
206 if (bsec_probe() != 0) {
207 panic();
208 }
209
210 /* Reset backup domain on cold boot cases */
211 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
212 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
213
214 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
215 0U) {
216 ;
217 }
218
219 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
220 }
221
222 /* Disable MCKPROT */
223 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
224
225 generic_delay_timer_init();
226
227 if (stm32mp1_clk_probe() < 0) {
228 panic();
229 }
230
231 if (stm32mp1_clk_init() < 0) {
232 panic();
233 }
234
235 stm32mp1_syscfg_init();
236
237 result = dt_get_stdout_uart_info(&dt_uart_info);
238
239 if ((result <= 0) ||
240 (dt_uart_info.status == 0U) ||
241 (dt_uart_info.clock < 0) ||
242 (dt_uart_info.reset < 0)) {
243 goto skip_console_init;
244 }
245
246 if (dt_set_stdout_pinctrl() != 0) {
247 goto skip_console_init;
248 }
249
250 stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
251
252 if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset,
253 RESET_TIMEOUT_US_1MS) != 0) {
254 panic();
255 }
256
257 udelay(2);
258
259 if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset,
260 RESET_TIMEOUT_US_1MS) != 0) {
261 panic();
262 }
263
264 mdelay(1);
265
266 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
267
268 if (console_stm32_register(dt_uart_info.base, clk_rate,
269 STM32MP_UART_BAUDRATE, &console) == 0) {
270 panic();
271 }
272
273 console_set_scope(&console, CONSOLE_FLAG_BOOT |
274 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
275
276 stm32mp_print_cpuinfo();
277
278 board_model = dt_get_board_model();
279 if (board_model != NULL) {
280 NOTICE("Model: %s\n", board_model);
281 }
282
283 stm32mp_print_boardinfo();
284
285 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
286 NOTICE("Bootrom authentication %s\n",
287 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
288 "failed" : "succeeded");
289 }
290
291 skip_console_init:
292 if (stm32_iwdg_init() < 0) {
293 panic();
294 }
295
296 stm32_iwdg_refresh();
297
298 result = stm32mp1_dbgmcu_freeze_iwdg2();
299 if (result != 0) {
300 INFO("IWDG2 freeze error : %i\n", result);
301 }
302
303 if (stm32_save_boot_interface(boot_context->boot_interface_selected,
304 boot_context->boot_interface_instance) !=
305 0) {
306 ERROR("Cannot save boot interface\n");
307 }
308
309 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
310 stm32mp1_auth_ops.verify_signature =
311 boot_context->bootrom_ecdsa_verify_signature;
312
313 stm32mp_init_auth(&stm32mp1_auth_ops);
314
315 stm32mp1_arch_security_setup();
316
317 print_reset_reason();
318
319 stm32mp_io_setup();
320 }
321
322 #if defined(AARCH32_SP_OPTEE)
323 /*******************************************************************************
324 * This function can be used by the platforms to update/use image
325 * information for given `image_id`.
326 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)327 int bl2_plat_handle_post_image_load(unsigned int image_id)
328 {
329 int err = 0;
330 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
331 bl_mem_params_node_t *bl32_mem_params;
332 bl_mem_params_node_t *pager_mem_params;
333 bl_mem_params_node_t *paged_mem_params;
334
335 assert(bl_mem_params != NULL);
336
337 switch (image_id) {
338 case BL32_IMAGE_ID:
339 bl_mem_params->ep_info.pc =
340 bl_mem_params->image_info.image_base;
341
342 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
343 assert(pager_mem_params != NULL);
344 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
345 pager_mem_params->image_info.image_max_size =
346 STM32MP_OPTEE_SIZE;
347
348 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
349 assert(paged_mem_params != NULL);
350 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
351 stm32mp_get_ddr_ns_size();
352 paged_mem_params->image_info.image_max_size =
353 STM32MP_DDR_S_SIZE;
354
355 err = parse_optee_header(&bl_mem_params->ep_info,
356 &pager_mem_params->image_info,
357 &paged_mem_params->image_info);
358 if (err) {
359 ERROR("OPTEE header parse error.\n");
360 panic();
361 }
362
363 /* Set optee boot info from parsed header data */
364 bl_mem_params->ep_info.pc =
365 pager_mem_params->image_info.image_base;
366 bl_mem_params->ep_info.args.arg0 =
367 paged_mem_params->image_info.image_base;
368 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
369 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
370 break;
371
372 case BL33_IMAGE_ID:
373 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
374 assert(bl32_mem_params != NULL);
375 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
376 break;
377
378 default:
379 /* Do nothing in default case */
380 break;
381 }
382
383 return err;
384 }
385
bl2_el3_plat_prepare_exit(void)386 void bl2_el3_plat_prepare_exit(void)
387 {
388 stm32mp1_security_setup();
389 }
390 #endif
391