1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <string.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <context.h>
14 #include <common/debug.h>
15 #include <lib/el3_runtime/context_mgmt.h>
16 #include <lib/xlat_tables/xlat_tables_v2.h>
17 #include <platform_def.h>
18 #include <plat/common/common_def.h>
19 #include <plat/common/platform.h>
20
21 #include "spm_common.h"
22 #include "spm_partition.h"
23 #include "spm_shim_private.h"
24
25 /* TODO: What is/is not common to any EL0 partition? */
26 /* Setup context of a EL0 MM Secure Partition */
spm_el0_sp_setup(sp_context_t * sp_ctx)27 void spm_el0_sp_setup(sp_context_t *sp_ctx)
28 {
29 cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
30
31 init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
32
33 /*
34 * MMU-related registers
35 * ---------------------
36 */
37 xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
38
39 uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
40
41 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
42 xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
43 EL1_EL0_REGIME);
44
45 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1,
46 mmu_cfg_params[MMU_CFG_MAIR]);
47
48 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1,
49 mmu_cfg_params[MMU_CFG_TCR]);
50
51 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1,
52 mmu_cfg_params[MMU_CFG_TTBR0]);
53
54 /* Setup SCTLR_EL1 */
55 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1);
56
57 sctlr_el1 |=
58 /*SCTLR_EL1_RES1 |*/
59 /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
60 SCTLR_UCI_BIT |
61 /* RW regions at xlat regime EL1&0 are forced to be XN. */
62 SCTLR_WXN_BIT |
63 /* Don't trap to EL1 execution of WFI or WFE at EL0. */
64 SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
65 /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
66 SCTLR_UCT_BIT |
67 /* Don't trap to EL1 execution of DZ ZVA at EL0. */
68 SCTLR_DZE_BIT |
69 /* Enable SP Alignment check for EL0 */
70 SCTLR_SA0_BIT |
71 /* Don't change PSTATE.PAN on taking an exception to EL1 */
72 SCTLR_SPAN_BIT |
73 /* Allow cacheable data and instr. accesses to normal memory. */
74 SCTLR_C_BIT | SCTLR_I_BIT |
75 /* Enable MMU. */
76 SCTLR_M_BIT
77 ;
78
79 sctlr_el1 &= ~(
80 /* Explicit data accesses at EL0 are little-endian. */
81 SCTLR_E0E_BIT |
82 /*
83 * Alignment fault checking disabled when at EL1 and EL0 as
84 * the UEFI spec permits unaligned accesses.
85 */
86 SCTLR_A_BIT |
87 /* Accesses to DAIF from EL0 are trapped to EL1. */
88 SCTLR_UMA_BIT
89 );
90
91 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
92
93 /*
94 * Setup other system registers
95 * ----------------------------
96 */
97
98 /* Shim Exception Vector Base Address */
99 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1,
100 SPM_SHIM_EXCEPTIONS_PTR);
101
102 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
103 EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
104
105 /*
106 * FPEN: Allow the Secure Partition to access FP/SIMD registers.
107 * Note that SPM will not do any saving/restoring of these registers on
108 * behalf of the SP. This falls under the SP's responsibility.
109 * TTA: Enable access to trace registers.
110 * ZEN (v8.2): Trap SVE instructions and access to SVE registers.
111 */
112 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CPACR_EL1,
113 CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
114
115 }
116
117
118 /* TODO: Split out common functionality to boot an SP. */
spm_sp_common_setup(sp_context_t * sp_ctx)119 void spm_sp_common_setup(sp_context_t *sp_ctx) {
120
121 }
122
123 /* TODO: SEL1 partition specific initialisation. */
spm_el1_sp_setup(sp_context_t * sp_ctx)124 void spm_el1_sp_setup(sp_context_t *sp_ctx)
125 {
126 /* TODO: Populate with EL1 specific initialisation. */
127
128 }