1 /*
2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/auth/auth_mod.h>
18 #include <drivers/console.h>
19 #include <lib/cpus/errata_report.h>
20 #include <lib/utils.h>
21 #include <plat/common/platform.h>
22 #include <smccc_helpers.h>
23 #include <tools_share/uuid.h>
24
25 #include "bl1_private.h"
26
27 static void bl1_load_bl2(void);
28
29 #if ENABLE_PAUTH
30 uint64_t bl1_apiakey[2];
31 #endif
32
33 /*******************************************************************************
34 * Helper utility to calculate the BL2 memory layout taking into consideration
35 * the BL1 RW data assuming that it is at the top of the memory layout.
36 ******************************************************************************/
bl1_calc_bl2_mem_layout(const meminfo_t * bl1_mem_layout,meminfo_t * bl2_mem_layout)37 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
38 meminfo_t *bl2_mem_layout)
39 {
40 assert(bl1_mem_layout != NULL);
41 assert(bl2_mem_layout != NULL);
42
43 /*
44 * Remove BL1 RW data from the scope of memory visible to BL2.
45 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
46 */
47 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
48 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
49 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
50
51 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
52 }
53
54 /*******************************************************************************
55 * Setup function for BL1.
56 ******************************************************************************/
bl1_setup(void)57 void bl1_setup(void)
58 {
59 /* Perform early platform-specific setup */
60 bl1_early_platform_setup();
61
62 /* Perform late platform-specific setup */
63 bl1_plat_arch_setup();
64
65 #if CTX_INCLUDE_PAUTH_REGS
66 /*
67 * Assert that the ARMv8.3-PAuth registers are present or an access
68 * fault will be triggered when they are being saved or restored.
69 */
70 assert(is_armv8_3_pauth_present());
71 #endif /* CTX_INCLUDE_PAUTH_REGS */
72 }
73
74 /*******************************************************************************
75 * Function to perform late architectural and platform specific initialization.
76 * It also queries the platform to load and run next BL image. Only called
77 * by the primary cpu after a cold boot.
78 ******************************************************************************/
bl1_main(void)79 void bl1_main(void)
80 {
81 unsigned int image_id;
82
83 /* Announce our arrival */
84 NOTICE(FIRMWARE_WELCOME_STR);
85 NOTICE("BL1: %s\n", version_string);
86 NOTICE("BL1: %s\n", build_message);
87
88 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
89
90 print_errata_status();
91
92 #if ENABLE_ASSERTIONS
93 u_register_t val;
94 /*
95 * Ensure that MMU/Caches and coherency are turned on
96 */
97 #ifdef __aarch64__
98 val = read_sctlr_el3();
99 #else
100 val = read_sctlr();
101 #endif
102 assert((val & SCTLR_M_BIT) != 0);
103 assert((val & SCTLR_C_BIT) != 0);
104 assert((val & SCTLR_I_BIT) != 0);
105 /*
106 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
107 * provided platform value
108 */
109 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
110 /*
111 * If CWG is zero, then no CWG information is available but we can
112 * at least check the platform value is less than the architectural
113 * maximum.
114 */
115 if (val != 0)
116 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
117 else
118 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
119 #endif /* ENABLE_ASSERTIONS */
120
121 /* Perform remaining generic architectural setup from EL3 */
122 bl1_arch_setup();
123
124 #if TRUSTED_BOARD_BOOT
125 /* Initialize authentication module */
126 auth_mod_init();
127 #endif /* TRUSTED_BOARD_BOOT */
128
129 /* Initialize the measured boot */
130 bl1_plat_mboot_init();
131
132 /* Perform platform setup in BL1. */
133 bl1_platform_setup();
134
135 #if ENABLE_PAUTH
136 /* Store APIAKey_EL1 key */
137 bl1_apiakey[0] = read_apiakeylo_el1();
138 bl1_apiakey[1] = read_apiakeyhi_el1();
139 #endif /* ENABLE_PAUTH */
140
141 /* Get the image id of next image to load and run. */
142 image_id = bl1_plat_get_next_image_id();
143
144 /*
145 * We currently interpret any image id other than
146 * BL2_IMAGE_ID as the start of firmware update.
147 */
148 if (image_id == BL2_IMAGE_ID)
149 bl1_load_bl2();
150 else
151 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
152
153 /* Teardown the measured boot driver */
154 bl1_plat_mboot_finish();
155
156 bl1_prepare_next_image(image_id);
157
158 console_flush();
159 }
160
161 /*******************************************************************************
162 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
163 * Called by the primary cpu after a cold boot.
164 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
165 * loader etc.
166 ******************************************************************************/
bl1_load_bl2(void)167 static void bl1_load_bl2(void)
168 {
169 image_desc_t *desc;
170 image_info_t *info;
171 int err;
172
173 /* Get the image descriptor */
174 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
175 assert(desc != NULL);
176
177 /* Get the image info */
178 info = &desc->image_info;
179 INFO("BL1: Loading BL2\n");
180
181 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
182 if (err != 0) {
183 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
184 plat_error_handler(err);
185 }
186
187 err = load_auth_image(BL2_IMAGE_ID, info);
188 if (err != 0) {
189 ERROR("Failed to load BL2 firmware.\n");
190 plat_error_handler(err);
191 }
192
193 /* Allow platform to handle image information. */
194 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
195 if (err != 0) {
196 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
197 plat_error_handler(err);
198 }
199
200 NOTICE("BL1: Booting BL2\n");
201 }
202
203 /*******************************************************************************
204 * Function called just before handing over to the next BL to inform the user
205 * about the boot progress. In debug mode, also print details about the BL
206 * image's execution context.
207 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)208 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
209 {
210 #ifdef __aarch64__
211 NOTICE("BL1: Booting BL31\n");
212 #else
213 NOTICE("BL1: Booting BL32\n");
214 #endif /* __aarch64__ */
215 print_entry_point_info(bl_ep_info);
216 }
217
218 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)219 void print_debug_loop_message(void)
220 {
221 NOTICE("BL1: Debug loop, spinning forever\n");
222 NOTICE("BL1: Please connect the debugger to continue\n");
223 }
224 #endif
225
226 /*******************************************************************************
227 * Top level handler for servicing BL1 SMCs.
228 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,unsigned int flags)229 u_register_t bl1_smc_handler(unsigned int smc_fid,
230 u_register_t x1,
231 u_register_t x2,
232 u_register_t x3,
233 u_register_t x4,
234 void *cookie,
235 void *handle,
236 unsigned int flags)
237 {
238 /* BL1 Service UUID */
239 DEFINE_SVC_UUID2(bl1_svc_uid,
240 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
241 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
242
243
244 #if TRUSTED_BOARD_BOOT
245 /*
246 * Dispatch FWU calls to FWU SMC handler and return its return
247 * value
248 */
249 if (is_fwu_fid(smc_fid)) {
250 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
251 handle, flags);
252 }
253 #endif
254
255 switch (smc_fid) {
256 case BL1_SMC_CALL_COUNT:
257 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
258
259 case BL1_SMC_UID:
260 SMC_UUID_RET(handle, bl1_svc_uid);
261
262 case BL1_SMC_VERSION:
263 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
264
265 default:
266 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
267 SMC_RET1(handle, SMC_UNK);
268 }
269 }
270
271 /*******************************************************************************
272 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
273 * compliance when invoking bl1_smc_handler.
274 ******************************************************************************/
bl1_smc_wrapper(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)275 u_register_t bl1_smc_wrapper(uint32_t smc_fid,
276 void *cookie,
277 void *handle,
278 unsigned int flags)
279 {
280 u_register_t x1, x2, x3, x4;
281
282 assert(handle != NULL);
283
284 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
285 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
286 }
287