1/*
2 * Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
16}
17
18
19SECTIONS
20{
21    . = BL2_BASE;
22    ASSERT(. == ALIGN(PAGE_SIZE),
23           "BL2_BASE address is not aligned on a page boundary.")
24
25#if SEPARATE_CODE_AND_RODATA
26    .text . : {
27        __TEXT_START__ = .;
28#if ENABLE_RME
29        *bl2_rme_entrypoint.o(.text*)
30#else /* ENABLE_RME */
31        *bl2_entrypoint.o(.text*)
32#endif /* ENABLE_RME */
33        *(SORT_BY_ALIGNMENT(.text*))
34        *(.vectors)
35        . = ALIGN(PAGE_SIZE);
36        __TEXT_END__ = .;
37     } >RAM
38
39     /* .ARM.extab and .ARM.exidx are only added because Clang need them */
40     .ARM.extab . : {
41        *(.ARM.extab* .gnu.linkonce.armextab.*)
42     } >RAM
43
44     .ARM.exidx . : {
45        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
46     } >RAM
47
48    .rodata . : {
49        __RODATA_START__ = .;
50        *(SORT_BY_ALIGNMENT(.rodata*))
51
52	RODATA_COMMON
53
54        . = ALIGN(PAGE_SIZE);
55        __RODATA_END__ = .;
56    } >RAM
57#else
58    ro . : {
59        __RO_START__ = .;
60        *bl2_entrypoint.o(.text*)
61        *(SORT_BY_ALIGNMENT(.text*))
62        *(SORT_BY_ALIGNMENT(.rodata*))
63
64	RODATA_COMMON
65
66        *(.vectors)
67        __RO_END_UNALIGNED__ = .;
68        /*
69         * Memory page(s) mapped to this section will be marked as
70         * read-only, executable.  No RW data from the next section must
71         * creep in.  Ensure the rest of the current memory page is unused.
72         */
73        . = ALIGN(PAGE_SIZE);
74        __RO_END__ = .;
75    } >RAM
76#endif
77
78    /*
79     * Define a linker symbol to mark start of the RW memory area for this
80     * image.
81     */
82    __RW_START__ = . ;
83
84    DATA_SECTION >RAM
85    STACK_SECTION >RAM
86    BSS_SECTION >RAM
87    XLAT_TABLE_SECTION >RAM
88
89#if USE_COHERENT_MEM
90    /*
91     * The base address of the coherent memory section must be page-aligned (4K)
92     * to guarantee that the coherent data are stored on their own pages and
93     * are not mixed with normal data.  This is required to set up the correct
94     * memory attributes for the coherent data page tables.
95     */
96    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
97        __COHERENT_RAM_START__ = .;
98        *(tzfw_coherent_mem)
99        __COHERENT_RAM_END_UNALIGNED__ = .;
100        /*
101         * Memory page(s) mapped to this section will be marked
102         * as device memory.  No other unexpected data must creep in.
103         * Ensure the rest of the current memory page is unused.
104         */
105        . = ALIGN(PAGE_SIZE);
106        __COHERENT_RAM_END__ = .;
107    } >RAM
108#endif
109
110    /*
111     * Define a linker symbol to mark end of the RW memory area for this
112     * image.
113     */
114    __RW_END__ = .;
115    __BL2_END__ = .;
116
117    __BSS_SIZE__ = SIZEOF(.bss);
118
119#if USE_COHERENT_MEM
120    __COHERENT_RAM_UNALIGNED_SIZE__ =
121        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
122#endif
123
124    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
125}
126