1/*
2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10
11	.globl	bl2u_vector_table
12	.globl	bl2u_entrypoint
13
14
15vector_base bl2u_vector_table
16	b	bl2u_entrypoint
17	b	report_exception	/* Undef */
18	b	report_exception	/* SVC call */
19	b	report_exception	/* Prefetch abort */
20	b	report_exception	/* Data abort */
21	b	report_exception	/* Reserved */
22	b	report_exception	/* IRQ */
23	b	report_exception	/* FIQ */
24
25
26func bl2u_entrypoint
27	/*---------------------------------------------
28	 * Save from r1 the extents of the trusted ram
29	 * available to BL2U for future use.
30	 * r0 is not currently used.
31	 * ---------------------------------------------
32	 */
33	mov	r11, r1
34	mov	r10, r2
35
36	/* ---------------------------------------------
37	 * Set the exception vector to something sane.
38	 * ---------------------------------------------
39	 */
40	ldr	r0, =bl2u_vector_table
41	stcopr	r0, VBAR
42	isb
43
44	/* --------------------------------------------------------
45	 * Enable the instruction cache - disable speculative loads
46	 * --------------------------------------------------------
47	 */
48	ldcopr	r0, SCTLR
49	orr	r0, r0, #SCTLR_I_BIT
50	bic	r0, r0, #SCTLR_DSSBS_BIT
51	stcopr	r0, SCTLR
52	isb
53
54	/* ---------------------------------------------
55	 * Since BL2U executes after BL1, it is assumed
56	 * here that BL1 has already has done the
57	 * necessary register initializations.
58	 * ---------------------------------------------
59	 */
60
61	/* ---------------------------------------------
62	 * Invalidate the RW memory used by the BL2U
63	 * image. This includes the data and NOBITS
64	 * sections. This is done to safeguard against
65	 * possible corruption of this memory by dirty
66	 * cache lines in a system cache as a result of
67	 * use by an earlier boot loader stage.
68	 * ---------------------------------------------
69	 */
70	ldr	r0, =__RW_START__
71	ldr	r1, =__RW_END__
72	sub	r1, r1, r0
73	bl	inv_dcache_range
74
75	/* ---------------------------------------------
76	 * Zero out NOBITS sections. There are 2 of them:
77	 *   - the .bss section;
78	 *   - the coherent memory section.
79	 * ---------------------------------------------
80	 */
81	ldr	r0, =__BSS_START__
82	ldr	r1, =__BSS_END__
83	sub 	r1, r1, r0
84	bl	zeromem
85
86	/* --------------------------------------------
87	 * Allocate a stack whose memory will be marked
88	 * as Normal-IS-WBWA when the MMU is enabled.
89	 * There is no risk of reading stale stack
90	 * memory after enabling the MMU as only the
91	 * primary cpu is running at the moment.
92	 * --------------------------------------------
93	 */
94	bl	plat_set_my_stack
95
96	/* ---------------------------------------------
97	 * Initialize the stack protector canary before
98	 * any C code is called.
99	 * ---------------------------------------------
100	 */
101#if STACK_PROTECTOR_ENABLED
102	bl	update_stack_protector_canary
103#endif
104
105	/* ---------------------------------------------
106	 * Perform early platform setup & platform
107	 * specific early arch. setup e.g. mmu setup
108	 * ---------------------------------------------
109	 */
110	mov	r0, r11
111	mov	r1, r10
112	bl	bl2u_early_platform_setup
113	bl	bl2u_plat_arch_setup
114
115	/* ---------------------------------------------
116	 * Jump to main function.
117	 * ---------------------------------------------
118	 */
119	bl	bl2u_main
120
121	/* ---------------------------------------------
122	 * Should never reach this point.
123	 * ---------------------------------------------
124	 */
125	no_ret	plat_panic_handler
126
127endfunc bl2u_entrypoint
128