1/* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 .globl bl2u_entrypoint 12 13 14func bl2u_entrypoint 15 /*--------------------------------------------- 16 * Store the extents of the tzram available to 17 * BL2U and other platform specific information 18 * for future use. x0 is currently not used. 19 * --------------------------------------------- 20 */ 21 mov x20, x1 22 mov x21, x2 23 24 /* --------------------------------------------- 25 * Set the exception vector to something sane. 26 * --------------------------------------------- 27 */ 28 adr x0, early_exceptions 29 msr vbar_el1, x0 30 isb 31 32 /* --------------------------------------------- 33 * Enable the SError interrupt now that the 34 * exception vectors have been setup. 35 * --------------------------------------------- 36 */ 37 msr daifclr, #DAIF_ABT_BIT 38 39 /* --------------------------------------------- 40 * Enable the instruction cache, stack pointer 41 * and data access alignment checks and disable 42 * speculative loads. 43 * --------------------------------------------- 44 */ 45 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 46 mrs x0, sctlr_el1 47 orr x0, x0, x1 48 bic x0, x0, #SCTLR_DSSBS_BIT 49 msr sctlr_el1, x0 50 isb 51 52 /* --------------------------------------------- 53 * Invalidate the RW memory used by the BL2U 54 * image. This includes the data and NOBITS 55 * sections. This is done to safeguard against 56 * possible corruption of this memory by dirty 57 * cache lines in a system cache as a result of 58 * use by an earlier boot loader stage. 59 * --------------------------------------------- 60 */ 61 adr x0, __RW_START__ 62 adr x1, __RW_END__ 63 sub x1, x1, x0 64 bl inv_dcache_range 65 66 /* --------------------------------------------- 67 * Zero out NOBITS sections. There are 2 of them: 68 * - the .bss section; 69 * - the coherent memory section. 70 * --------------------------------------------- 71 */ 72 adrp x0, __BSS_START__ 73 add x0, x0, :lo12:__BSS_START__ 74 adrp x1, __BSS_END__ 75 add x1, x1, :lo12:__BSS_END__ 76 sub x1, x1, x0 77 bl zeromem 78 79 /* -------------------------------------------- 80 * Allocate a stack whose memory will be marked 81 * as Normal-IS-WBWA when the MMU is enabled. 82 * There is no risk of reading stale stack 83 * memory after enabling the MMU as only the 84 * primary cpu is running at the moment. 85 * -------------------------------------------- 86 */ 87 bl plat_set_my_stack 88 89 /* --------------------------------------------- 90 * Initialize the stack protector canary before 91 * any C code is called. 92 * --------------------------------------------- 93 */ 94#if STACK_PROTECTOR_ENABLED 95 bl update_stack_protector_canary 96#endif 97 98 /* --------------------------------------------- 99 * Perform early platform setup & platform 100 * specific early arch. setup e.g. mmu setup 101 * --------------------------------------------- 102 */ 103 mov x0, x20 104 mov x1, x21 105 bl bl2u_early_platform_setup 106 bl bl2u_plat_arch_setup 107 108#if ENABLE_PAUTH 109 /* --------------------------------------------- 110 * Program APIAKey_EL1 111 * and enable pointer authentication. 112 * --------------------------------------------- 113 */ 114 bl pauth_init_enable_el1 115#endif 116 117 /* --------------------------------------------- 118 * Jump to bl2u_main function. 119 * --------------------------------------------- 120 */ 121 bl bl2u_main 122 123 /* --------------------------------------------- 124 * Should never reach this point. 125 * --------------------------------------------- 126 */ 127 no_ret plat_panic_handler 128 129endfunc bl2u_entrypoint 130