1#
2# Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7ifneq (${ARCH}, aarch32)
8	$(error SP_MIN is only supported on AArch32 platforms)
9endif
10
11include lib/extensions/amu/amu.mk
12include lib/psci/psci_lib.mk
13
14INCLUDES		+=	-Iinclude/bl32/sp_min
15
16BL32_SOURCES		+=	bl32/sp_min/sp_min_main.c		\
17				bl32/sp_min/aarch32/entrypoint.S	\
18				common/runtime_svc.c			\
19				plat/common/aarch32/plat_sp_min_common.c\
20				services/std_svc/std_svc_setup.c	\
21				${PSCI_LIB_SOURCES}
22
23ifeq (${DISABLE_MTPMU},1)
24BL32_SOURCES		+=	lib/extensions/mtpmu/aarch32/mtpmu.S
25endif
26
27ifeq (${ENABLE_PMF}, 1)
28BL32_SOURCES		+=	lib/pmf/pmf_main.c
29endif
30
31ifeq (${ENABLE_AMU},1)
32BL32_SOURCES		+=	${AMU_SOURCES}
33endif
34
35ifeq (${WORKAROUND_CVE_2017_5715},1)
36BL32_SOURCES		+=	bl32/sp_min/wa_cve_2017_5715_bpiall.S	\
37				bl32/sp_min/wa_cve_2017_5715_icache_inv.S
38endif
39
40ifeq (${TRNG_SUPPORT},1)
41BL32_SOURCES		+=	services/std_svc/trng/trng_main.c	\
42				services/std_svc/trng/trng_entropy_pool.c
43endif
44
45ifeq (${ENABLE_SYS_REG_TRACE_FOR_NS},1)
46BL32_SOURCES		+=	lib/extensions/sys_reg_trace/aarch32/sys_reg_trace.c
47endif
48
49ifeq (${ENABLE_TRF_FOR_NS},1)
50BL32_SOURCES		+=	lib/extensions/trf/aarch32/trf.c
51endif
52
53BL32_LINKERFILE	:=	bl32/sp_min/sp_min.ld.S
54
55# Include the platform-specific SP_MIN Makefile
56# If no platform-specific SP_MIN Makefile exists, it means SP_MIN is not supported
57# on this platform.
58SP_MIN_PLAT_MAKEFILE := $(wildcard ${PLAT_DIR}/sp_min/sp_min-${PLAT}.mk)
59ifeq (,${SP_MIN_PLAT_MAKEFILE})
60  $(error SP_MIN is not supported on platform ${PLAT})
61else
62  include ${SP_MIN_PLAT_MAKEFILE}
63endif
64
65RESET_TO_SP_MIN	:= 0
66$(eval $(call add_define,RESET_TO_SP_MIN))
67$(eval $(call assert_boolean,RESET_TO_SP_MIN))
68
69# Flag to allow SP_MIN to handle FIQ interrupts in monitor mode. The platform
70# port is free to override this value. It is default disabled.
71SP_MIN_WITH_SECURE_FIQ 	?= 0
72$(eval $(call add_define,SP_MIN_WITH_SECURE_FIQ))
73$(eval $(call assert_boolean,SP_MIN_WITH_SECURE_FIQ))
74