1 /*
2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <inttypes.h>
9
10 #include <platform_def.h>
11
12 #include <arch_helpers.h>
13 #include <bl32/tsp/tsp.h>
14 #include <common/debug.h>
15 #include <plat/common/platform.h>
16
17 #include "tsp_private.h"
18
19 /*******************************************************************************
20 * This function updates the TSP statistics for S-EL1 interrupts handled
21 * synchronously i.e the ones that have been handed over by the TSPD. It also
22 * keeps count of the number of times control was passed back to the TSPD
23 * after handling the interrupt. In the future it will be possible that the
24 * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
25 * return execution. This statistic will be useful to distinguish between these
26 * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
27 * contains the address of the instruction in normal world where this S-EL1
28 * interrupt was generated.
29 ******************************************************************************/
tsp_update_sync_sel1_intr_stats(uint32_t type,uint64_t elr_el3)30 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
31 {
32 uint32_t linear_id = plat_my_core_pos();
33
34 tsp_stats[linear_id].sync_sel1_intr_count++;
35 if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
36 tsp_stats[linear_id].sync_sel1_intr_ret_count++;
37
38 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
39 spin_lock(&console_lock);
40 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n",
41 read_mpidr(), elr_el3);
42 VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
43 " %d sync s-el1 interrupt returns\n",
44 read_mpidr(),
45 tsp_stats[linear_id].sync_sel1_intr_count,
46 tsp_stats[linear_id].sync_sel1_intr_ret_count);
47 spin_unlock(&console_lock);
48 #endif
49 }
50
51 /******************************************************************************
52 * This function is invoked when a non S-EL1 interrupt is received and causes
53 * the preemption of TSP. This function returns TSP_PREEMPTED and results
54 * in the control being handed over to EL3 for handling the interrupt.
55 *****************************************************************************/
tsp_handle_preemption(void)56 int32_t tsp_handle_preemption(void)
57 {
58 uint32_t linear_id = plat_my_core_pos();
59
60 tsp_stats[linear_id].preempt_intr_count++;
61 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
62 spin_lock(&console_lock);
63 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
64 read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
65 spin_unlock(&console_lock);
66 #endif
67 return TSP_PREEMPTED;
68 }
69
70 /*******************************************************************************
71 * TSP interrupt handler is called as a part of both synchronous and
72 * asynchronous handling of TSP interrupts. Currently the physical timer
73 * interrupt is the only S-EL1 interrupt that this handler expects. It returns
74 * 0 upon successfully handling the expected interrupt and all other
75 * interrupts are treated as normal world or EL3 interrupts.
76 ******************************************************************************/
tsp_common_int_handler(void)77 int32_t tsp_common_int_handler(void)
78 {
79 uint32_t linear_id = plat_my_core_pos(), id;
80
81 /*
82 * Get the highest priority pending interrupt id and see if it is the
83 * secure physical generic timer interrupt in which case, handle it.
84 * Otherwise throw this interrupt at the EL3 firmware.
85 *
86 * There is a small time window between reading the highest priority
87 * pending interrupt and acknowledging it during which another
88 * interrupt of higher priority could become the highest pending
89 * interrupt. This is not expected to happen currently for TSP.
90 */
91 id = plat_ic_get_pending_interrupt_id();
92
93 /* TSP can only handle the secure physical timer interrupt */
94 if (id != TSP_IRQ_SEC_PHY_TIMER)
95 return tsp_handle_preemption();
96
97 /*
98 * Acknowledge and handle the secure timer interrupt. Also sanity check
99 * if it has been preempted by another interrupt through an assertion.
100 */
101 id = plat_ic_acknowledge_interrupt();
102 assert(id == TSP_IRQ_SEC_PHY_TIMER);
103 tsp_generic_timer_handler();
104 plat_ic_end_of_interrupt(id);
105
106 /* Update the statistics and print some messages */
107 tsp_stats[linear_id].sel1_intr_count++;
108 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE
109 spin_lock(&console_lock);
110 VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
111 read_mpidr(), id);
112 VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
113 read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
114 spin_unlock(&console_lock);
115 #endif
116 return 0;
117 }
118