1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 31 The descriptions in this chapter are for the Arm TrustZone architecture. 32 For changes to the firmware design for the 33 `Arm Confidential Compute Architecture (Arm CCA)`_ please refer to the 34 chapter :ref:`Realm Management Extension (RME)`. 35 36Cold boot 37--------- 38 39The cold boot path starts when the platform is physically turned on. If 40``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 41primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 42CPU is chosen through platform-specific means. The cold boot path is mainly 43executed by the primary CPU, other than essential CPU initialization executed by 44all CPUs. The secondary CPUs are kept in a safe platform-specific state until 45the primary CPU has performed enough initialization to boot them. 46 47Refer to the :ref:`CPU Reset` for more information on the effect of the 48``COLD_BOOT_SINGLE_CPU`` platform build option. 49 50The cold boot path in this implementation of TF-A depends on the execution 51state. For AArch64, it is divided into five steps (in order of execution): 52 53- Boot Loader stage 1 (BL1) *AP Trusted ROM* 54- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 55- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 56- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 58 59For AArch32, it is divided into four steps (in order of execution): 60 61- Boot Loader stage 1 (BL1) *AP Trusted ROM* 62- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 63- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 64- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 65 66Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 67combination of the following types of memory regions. Each bootloader stage uses 68one or more of these memory regions. 69 70- Regions accessible from both non-secure and secure states. For example, 71 non-trusted SRAM, ROM and DRAM. 72- Regions accessible from only the secure state. For example, trusted SRAM and 73 ROM. The FVPs also implement the trusted DRAM which is statically 74 configured. Additionally, the Base FVPs and Juno development platform 75 configure the TrustZone Controller (TZC) to create a region in the DRAM 76 which is accessible only from the secure state. 77 78The sections below provide the following details: 79 80- dynamic configuration of Boot Loader stages 81- initialization and execution of the first three stages during cold boot 82- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 83 AArch32) entrypoint requirements for use by alternative Trusted Boot 84 Firmware in place of the provided BL1 and BL2 85 86Dynamic Configuration during cold boot 87~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 88 89Each of the Boot Loader stages may be dynamically configured if required by the 90platform. The Boot Loader stage may optionally specify a firmware 91configuration file and/or hardware configuration file as listed below: 92 93- FW_CONFIG - The firmware configuration file. Holds properties shared across 94 all BLx images. 95 An example is the "dtb-registry" node, which contains the information about 96 the other device tree configurations (load-address, size, image_id). 97- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 98 stages and also by the Normal World Rich OS. 99- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 100 and BL2. 101- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 102- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 103 (BL32). 104- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 105 firmware (BL33). 106 107The Arm development platforms use the Flattened Device Tree format for the 108dynamic configuration files. 109 110Each Boot Loader stage can pass up to 4 arguments via registers to the next 111stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 112Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 113arguments are platform defined. The Arm development platforms use the following 114convention: 115 116- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 117 structure contains the memory layout available to BL2. 118- When dynamic configuration files are present, the firmware configuration for 119 the next Boot Loader stage is populated in the first available argument and 120 the generic hardware configuration is passed the next available argument. 121 For example, 122 123 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 124 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 125 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 126 BL2. Note, ``arg1`` is already used for meminfo_t. 127 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 128 to BL31. Note, ``arg0`` is used to pass the list of executable images. 129 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 130 passed in ``arg2`` to BL31. 131 - For other BL3x images, if the firmware configuration file is loaded by 132 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 133 then its address is passed in ``arg1``. 134 135BL1 136~~~ 137 138This stage begins execution from the platform's reset vector at EL3. The reset 139address is platform dependent but it is usually located in a Trusted ROM area. 140The BL1 data section is copied to trusted SRAM at runtime. 141 142On the Arm development platforms, BL1 code starts execution from the reset 143vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 144to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 145 146The functionality implemented by this stage is as follows. 147 148Determination of boot path 149^^^^^^^^^^^^^^^^^^^^^^^^^^ 150 151Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 152boot and a cold boot. This is done using platform-specific mechanisms (see the 153``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 154of a warm boot, a CPU is expected to continue execution from a separate 155entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 156platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 157the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 158path as described in the following sections. 159 160This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 161:ref:`CPU Reset` for more information on the effect of the 162``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 163 164Architectural initialization 165^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 166 167BL1 performs minimal architectural initialization as follows. 168 169- Exception vectors 170 171 BL1 sets up simple exception vectors for both synchronous and asynchronous 172 exceptions. The default behavior upon receiving an exception is to populate 173 a status code in the general purpose register ``X0/R0`` and call the 174 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 175 status code is one of: 176 177 For AArch64: 178 179 :: 180 181 0x0 : Synchronous exception from Current EL with SP_EL0 182 0x1 : IRQ exception from Current EL with SP_EL0 183 0x2 : FIQ exception from Current EL with SP_EL0 184 0x3 : System Error exception from Current EL with SP_EL0 185 0x4 : Synchronous exception from Current EL with SP_ELx 186 0x5 : IRQ exception from Current EL with SP_ELx 187 0x6 : FIQ exception from Current EL with SP_ELx 188 0x7 : System Error exception from Current EL with SP_ELx 189 0x8 : Synchronous exception from Lower EL using aarch64 190 0x9 : IRQ exception from Lower EL using aarch64 191 0xa : FIQ exception from Lower EL using aarch64 192 0xb : System Error exception from Lower EL using aarch64 193 0xc : Synchronous exception from Lower EL using aarch32 194 0xd : IRQ exception from Lower EL using aarch32 195 0xe : FIQ exception from Lower EL using aarch32 196 0xf : System Error exception from Lower EL using aarch32 197 198 For AArch32: 199 200 :: 201 202 0x10 : User mode 203 0x11 : FIQ mode 204 0x12 : IRQ mode 205 0x13 : SVC mode 206 0x16 : Monitor mode 207 0x17 : Abort mode 208 0x1a : Hypervisor mode 209 0x1b : Undefined mode 210 0x1f : System mode 211 212 The ``plat_report_exception()`` implementation on the Arm FVP port programs 213 the Versatile Express System LED register in the following format to 214 indicate the occurrence of an unexpected exception: 215 216 :: 217 218 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 219 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 220 For AArch32 it is always 0x0 221 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 222 of the status code 223 224 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 225 CLCD window of the FVP. 226 227 BL1 does not expect to receive any exceptions other than the SMC exception. 228 For the latter, BL1 installs a simple stub. The stub expects to receive a 229 limited set of SMC types (determined by their function IDs in the general 230 purpose register ``X0/R0``): 231 232 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 233 to EL3 Runtime Software. 234 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 235 Design Guide are supported for AArch64 only. These SMCs are currently 236 not supported when BL1 is built for AArch32. 237 238 Any other SMC leads to an assertion failure. 239 240- CPU initialization 241 242 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 243 specific reset handler function (see the section: "CPU specific operations 244 framework"). 245 246- Control register setup (for AArch64) 247 248 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 249 bit. Alignment and stack alignment checking is enabled by setting the 250 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 251 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 252 253 - ``SCR_EL3``. The register width of the next lower exception level is set 254 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 255 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 256 also set to disable instruction fetches from Non-secure memory when in 257 secure state. 258 259 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 260 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 261 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 262 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 263 Instructions that access the registers associated with Floating Point 264 and Advanced SIMD execution are configured to not trap to EL3 by 265 clearing the ``CPTR_EL3.TFP`` bit. 266 267 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 268 mask bit. 269 270 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 271 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 272 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 273 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 274 disable AArch32 Secure self-hosted privileged debug from S-EL1. 275 276- Control register setup (for AArch32) 277 278 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 279 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 280 Exception endianness is set to little-endian by clearing the 281 ``SCTLR.EE`` bit. 282 283 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 284 Non-secure memory when in secure state. 285 286 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 287 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 288 is configured not to trap to undefined mode by clearing the 289 ``CPACR.TRCDIS`` bit. 290 291 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 292 system register access to implemented trace registers. 293 294 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 295 functionality from all Exception levels. 296 297 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 298 the Asynchronous data abort interrupt mask bit. 299 300 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 301 self-hosted privileged debug. 302 303Platform initialization 304^^^^^^^^^^^^^^^^^^^^^^^ 305 306On Arm platforms, BL1 performs the following platform initializations: 307 308- Enable the Trusted Watchdog. 309- Initialize the console. 310- Configure the Interconnect to enable hardware coherency. 311- Enable the MMU and map the memory it needs to access. 312- Configure any required platform storage to load the next bootloader image 313 (BL2). 314- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 315 load it to the platform defined address and make it available to BL2 via 316 ``arg0``. 317- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 318 and NS-BL2U firmware update images. 319 320Firmware Update detection and execution 321^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 322 323After performing platform setup, BL1 common code calls 324``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 325required or to proceed with the normal boot process. If the platform code 326returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 327in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 328required and execution passes to the first image in the 329:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 330of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 331contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 332execution state of the next image. 333 334BL2 image load and execution 335^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 336 337In the normal boot flow, BL1 execution continues as follows: 338 339#. BL1 prints the following string from the primary CPU to indicate successful 340 execution of the BL1 stage: 341 342 :: 343 344 "Booting Trusted Firmware" 345 346#. BL1 loads a BL2 raw binary image from platform storage, at a 347 platform-specific base address. Prior to the load, BL1 invokes 348 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 349 use the image information. If the BL2 image file is not present or if 350 there is not enough free trusted SRAM the following error message is 351 printed: 352 353 :: 354 355 "Failed to load BL2 firmware." 356 357#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 358 for platforms to take further action after image load. This function must 359 populate the necessary arguments for BL2, which may also include the memory 360 layout. Further description of the memory layout can be found later 361 in this document. 362 363#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 364 Secure SVC mode (for AArch32), starting from its load address. 365 366BL2 367~~~ 368 369BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 370SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 371base address (more information can be found later in this document). 372The functionality implemented by BL2 is as follows. 373 374Architectural initialization 375^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 376 377For AArch64, BL2 performs the minimal architectural initialization required 378for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 379access to Floating Point and Advanced SIMD registers by setting the 380``CPACR.FPEN`` bits. 381 382For AArch32, the minimal architectural initialization required for subsequent 383stages of TF-A and normal world software is taken care of in BL1 as both BL1 384and BL2 execute at PL1. 385 386Platform initialization 387^^^^^^^^^^^^^^^^^^^^^^^ 388 389On Arm platforms, BL2 performs the following platform initializations: 390 391- Initialize the console. 392- Configure any required platform storage to allow loading further bootloader 393 images. 394- Enable the MMU and map the memory it needs to access. 395- Perform platform security setup to allow access to controlled components. 396- Reserve some memory for passing information to the next bootloader image 397 EL3 Runtime Software and populate it. 398- Define the extents of memory available for loading each subsequent 399 bootloader image. 400- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 401 then parse it. 402 403Image loading in BL2 404^^^^^^^^^^^^^^^^^^^^ 405 406BL2 generic code loads the images based on the list of loadable images 407provided by the platform. BL2 passes the list of executable images 408provided by the platform to the next handover BL image. 409 410The list of loadable images provided by the platform may also contain 411dynamic configuration files. The files are loaded and can be parsed as 412needed in the ``bl2_plat_handle_post_image_load()`` function. These 413configuration files can be passed to next Boot Loader stages as arguments 414by updating the corresponding entrypoint information in this function. 415 416SCP_BL2 (System Control Processor Firmware) image load 417^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 418 419Some systems have a separate System Control Processor (SCP) for power, clock, 420reset and system control. BL2 loads the optional SCP_BL2 image from platform 421storage into a platform-specific region of secure memory. The subsequent 422handling of SCP_BL2 is platform specific. For example, on the Juno Arm 423development platform port the image is transferred into SCP's internal memory 424using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 425memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 426for BL2 execution to continue. 427 428EL3 Runtime Software image load 429^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 430 431BL2 loads the EL3 Runtime Software image from platform storage into a platform- 432specific address in trusted SRAM. If there is not enough memory to load the 433image or image is missing it leads to an assertion failure. 434 435AArch64 BL32 (Secure-EL1 Payload) image load 436^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 437 438BL2 loads the optional BL32 image from platform storage into a platform- 439specific region of secure memory. The image executes in the secure world. BL2 440relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 441populates a platform-specific area of memory with the entrypoint/load-address 442of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 443for entry into BL32 is not determined by BL2, it is initialized by the 444Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 445managing interaction with BL32. This information is passed to BL31. 446 447BL33 (Non-trusted Firmware) image load 448^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 449 450BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 451platform storage into non-secure memory as defined by the platform. 452 453BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 454initialization is complete. Hence, BL2 populates a platform-specific area of 455memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 456normal world software image. The entrypoint is the load address of the BL33 457image. The ``SPSR`` is determined as specified in Section 5.13 of the 458`Power State Coordination Interface PDD`_. This information is passed to the 459EL3 Runtime Software. 460 461AArch64 BL31 (EL3 Runtime Software) execution 462^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 463 464BL2 execution continues as follows: 465 466#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 467 BL31 entrypoint. The exception is handled by the SMC exception handler 468 installed by BL1. 469 470#. BL1 turns off the MMU and flushes the caches. It clears the 471 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 472 and invalidates the TLBs. 473 474#. BL1 passes control to BL31 at the specified entrypoint at EL3. 475 476Running BL2 at EL3 execution level 477~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 478 479Some platforms have a non-TF-A Boot ROM that expects the next boot stage 480to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 481as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 482this waste, a special mode enables BL2 to execute at EL3, which allows 483a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 484when the build flag BL2_AT_EL3 is enabled. The main differences in this 485mode are: 486 487#. BL2 includes the reset code and the mailbox mechanism to differentiate 488 cold boot and warm boot. It runs at EL3 doing the arch 489 initialization required for EL3. 490 491#. BL2 does not receive the meminfo information from BL1 anymore. This 492 information can be passed by the Boot ROM or be internal to the 493 BL2 image. 494 495#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 496 instead of invoking the RUN_IMAGE SMC call. 497 498 499We assume 3 different types of BootROM support on the platform: 500 501#. The Boot ROM always jumps to the same address, for both cold 502 and warm boot. In this case, we will need to keep a resident part 503 of BL2 whose memory cannot be reclaimed by any other image. The 504 linker script defines the symbols __TEXT_RESIDENT_START__ and 505 __TEXT_RESIDENT_END__ that allows the platform to configure 506 correctly the memory map. 507#. The platform has some mechanism to indicate the jump address to the 508 Boot ROM. Platform code can then program the jump address with 509 psci_warmboot_entrypoint during cold boot. 510#. The platform has some mechanism to program the reset address using 511 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 512 program the reset address with psci_warmboot_entrypoint during 513 cold boot, bypassing the boot ROM for warm boot. 514 515In the last 2 cases, no part of BL2 needs to remain resident at 516runtime. In the first 2 cases, we expect the Boot ROM to be able to 517differentiate between warm and cold boot, to avoid loading BL2 again 518during warm boot. 519 520This functionality can be tested with FVP loading the image directly 521in memory and changing the address where the system jumps at reset. 522For example: 523 524 -C cluster0.cpu0.RVBAR=0x4022000 525 --data cluster0.cpu0=bl2.bin@0x4022000 526 527With this configuration, FVP is like a platform of the first case, 528where the Boot ROM jumps always to the same address. For simplification, 529BL32 is loaded in DRAM in this case, to avoid other images reclaiming 530BL2 memory. 531 532 533AArch64 BL31 534~~~~~~~~~~~~ 535 536The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 537EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 538loaded at a platform-specific base address (more information can be found later 539in this document). The functionality implemented by BL31 is as follows. 540 541Architectural initialization 542^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 543 544Currently, BL31 performs a similar architectural initialization to BL1 as 545far as system register settings are concerned. Since BL1 code resides in ROM, 546architectural initialization in BL31 allows override of any previous 547initialization done by BL1. 548 549BL31 initializes the per-CPU data framework, which provides a cache of 550frequently accessed per-CPU data optimised for fast, concurrent manipulation 551on different CPUs. This buffer includes pointers to per-CPU contexts, crash 552buffer, CPU reset and power down operations, PSCI data, platform data and so on. 553 554It then replaces the exception vectors populated by BL1 with its own. BL31 555exception vectors implement more elaborate support for handling SMCs since this 556is the only mechanism to access the runtime services implemented by BL31 (PSCI 557for example). BL31 checks each SMC for validity as specified by the 558`SMC Calling Convention`_ before passing control to the required SMC 559handler routine. 560 561BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 562counter, which is provided by the platform. 563 564Platform initialization 565^^^^^^^^^^^^^^^^^^^^^^^ 566 567BL31 performs detailed platform initialization, which enables normal world 568software to function correctly. 569 570On Arm platforms, this consists of the following: 571 572- Initialize the console. 573- Configure the Interconnect to enable hardware coherency. 574- Enable the MMU and map the memory it needs to access. 575- Initialize the generic interrupt controller. 576- Initialize the power controller device. 577- Detect the system topology. 578 579Runtime services initialization 580^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 581 582BL31 is responsible for initializing the runtime services. One of them is PSCI. 583 584As part of the PSCI initializations, BL31 detects the system topology. It also 585initializes the data structures that implement the state machine used to track 586the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 587``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 588that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 589initializes the locks that protect them. BL31 accesses the state of a CPU or 590cluster immediately after reset and before the data cache is enabled in the 591warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 592therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 593 594The runtime service framework and its initialization is described in more 595detail in the "EL3 runtime services framework" section below. 596 597Details about the status of the PSCI implementation are provided in the 598"Power State Coordination Interface" section below. 599 600AArch64 BL32 (Secure-EL1 Payload) image initialization 601^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 602 603If a BL32 image is present then there must be a matching Secure-EL1 Payload 604Dispatcher (SPD) service (see later for details). During initialization 605that service must register a function to carry out initialization of BL32 606once the runtime services are fully initialized. BL31 invokes such a 607registered function to initialize BL32 before running BL33. This initialization 608is not necessary for AArch32 SPs. 609 610Details on BL32 initialization and the SPD's role are described in the 611:ref:`firmware_design_sel1_spd` section below. 612 613BL33 (Non-trusted Firmware) execution 614^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 615 616EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 617world cold boot, ensuring that no secure state information finds its way into 618the non-secure execution state. EL3 Runtime Software uses the entrypoint 619information provided by BL2 to jump to the Non-trusted firmware image (BL33) 620at the highest available Exception Level (EL2 if available, otherwise EL1). 621 622Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 623~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 624 625Some platforms have existing implementations of Trusted Boot Firmware that 626would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 627firmware architecture it is important to provide a fully documented and stable 628interface between the Trusted Boot Firmware and BL31. 629 630Future changes to the BL31 interface will be done in a backwards compatible 631way, and this enables these firmware components to be independently enhanced/ 632updated to develop and exploit new functionality. 633 634Required CPU state when calling ``bl31_entrypoint()`` during cold boot 635^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 636 637This function must only be called by the primary CPU. 638 639On entry to this function the calling primary CPU must be executing in AArch64 640EL3, little-endian data access, and all interrupt sources masked: 641 642:: 643 644 PSTATE.EL = 3 645 PSTATE.RW = 1 646 PSTATE.DAIF = 0xf 647 SCTLR_EL3.EE = 0 648 649X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 650platform code in BL31: 651 652:: 653 654 X0 : Reserved for common TF-A information 655 X1 : Platform specific information 656 657BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 658these will be zero filled prior to invoking platform setup code. 659 660Use of the X0 and X1 parameters 661''''''''''''''''''''''''''''''' 662 663The parameters are platform specific and passed from ``bl31_entrypoint()`` to 664``bl31_early_platform_setup()``. The value of these parameters is never directly 665used by the common BL31 code. 666 667The convention is that ``X0`` conveys information regarding the BL31, BL32 and 668BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 669platform specific purpose. This convention allows platforms which use TF-A's 670BL1 and BL2 images to transfer additional platform specific information from 671Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 672pass a ``bl31_params`` structure. 673 674BL31 common and SPD initialization code depends on image and entrypoint 675information about BL33 and BL32, which is provided via BL31 platform APIs. 676This information is required until the start of execution of BL33. This 677information can be provided in a platform defined manner, e.g. compiled into 678the platform code in BL31, or provided in a platform defined memory location 679by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 680Cold boot Initialization parameters. This data may need to be cleaned out of 681the CPU caches if it is provided by an earlier boot stage and then accessed by 682BL31 platform code before the caches are enabled. 683 684TF-A's BL2 implementation passes a ``bl31_params`` structure in 685``X0`` and the Arm development platforms interpret this in the BL31 platform 686code. 687 688MMU, Data caches & Coherency 689'''''''''''''''''''''''''''' 690 691BL31 does not depend on the enabled state of the MMU, data caches or 692interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 693on entry, these should be enabled during ``bl31_plat_arch_setup()``. 694 695Data structures used in the BL31 cold boot interface 696'''''''''''''''''''''''''''''''''''''''''''''''''''' 697 698These structures are designed to support compatibility and independent 699evolution of the structures and the firmware images. For example, a version of 700BL31 that can interpret the BL3x image information from different versions of 701BL2, a platform that uses an extended entry_point_info structure to convey 702additional register information to BL31, or a ELF image loader that can convey 703more details about the firmware images. 704 705To support these scenarios the structures are versioned and sized, which enables 706BL31 to detect which information is present and respond appropriately. The 707``param_header`` is defined to capture this information: 708 709.. code:: c 710 711 typedef struct param_header { 712 uint8_t type; /* type of the structure */ 713 uint8_t version; /* version of this structure */ 714 uint16_t size; /* size of this structure in bytes */ 715 uint32_t attr; /* attributes: unused bits SBZ */ 716 } param_header_t; 717 718The structures using this format are ``entry_point_info``, ``image_info`` and 719``bl31_params``. The code that allocates and populates these structures must set 720the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 721to simplify this action. 722 723Required CPU state for BL31 Warm boot initialization 724^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 725 726When requesting a CPU power-on, or suspending a running CPU, TF-A provides 727the platform power management code with a Warm boot initialization 728entry-point, to be invoked by the CPU immediately after the reset handler. 729On entry to the Warm boot initialization function the calling CPU must be in 730AArch64 EL3, little-endian data access and all interrupt sources masked: 731 732:: 733 734 PSTATE.EL = 3 735 PSTATE.RW = 1 736 PSTATE.DAIF = 0xf 737 SCTLR_EL3.EE = 0 738 739The PSCI implementation will initialize the processor state and ensure that the 740platform power management code is then invoked as required to initialize all 741necessary system, cluster and CPU resources. 742 743AArch32 EL3 Runtime Software entrypoint interface 744~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 745 746To enable this firmware architecture it is important to provide a fully 747documented and stable interface between the Trusted Boot Firmware and the 748AArch32 EL3 Runtime Software. 749 750Future changes to the entrypoint interface will be done in a backwards 751compatible way, and this enables these firmware components to be independently 752enhanced/updated to develop and exploit new functionality. 753 754Required CPU state when entering during cold boot 755^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 756 757This function must only be called by the primary CPU. 758 759On entry to this function the calling primary CPU must be executing in AArch32 760EL3, little-endian data access, and all interrupt sources masked: 761 762:: 763 764 PSTATE.AIF = 0x7 765 SCTLR.EE = 0 766 767R0 and R1 are used to pass information from the Trusted Boot Firmware to the 768platform code in AArch32 EL3 Runtime Software: 769 770:: 771 772 R0 : Reserved for common TF-A information 773 R1 : Platform specific information 774 775Use of the R0 and R1 parameters 776''''''''''''''''''''''''''''''' 777 778The parameters are platform specific and the convention is that ``R0`` conveys 779information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 780can be used for other platform specific purpose. This convention allows 781platforms which use TF-A's BL1 and BL2 images to transfer additional platform 782specific information from Secure Boot without conflicting with future 783evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 784 785The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 786information can be obtained in a platform defined manner, e.g. compiled into 787the AArch32 EL3 Runtime Software, or provided in a platform defined memory 788location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 789via the Cold boot Initialization parameters. This data may need to be cleaned 790out of the CPU caches if it is provided by an earlier boot stage and then 791accessed by AArch32 EL3 Runtime Software before the caches are enabled. 792 793When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 794``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 795Software platform code. 796 797MMU, Data caches & Coherency 798'''''''''''''''''''''''''''' 799 800AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 801data caches or interconnect coherency in its entrypoint. They must be explicitly 802enabled if required. 803 804Data structures used in cold boot interface 805''''''''''''''''''''''''''''''''''''''''''' 806 807The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 808of ``bl31_params``. The ``bl_params`` structure is based on the convention 809described in AArch64 BL31 cold boot interface section. 810 811Required CPU state for warm boot initialization 812^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 813 814When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 815Runtime Software must ensure execution of a warm boot initialization entrypoint. 816If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 817then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 818boot entrypoint by arranging for the BL1 platform function, 819plat_get_my_entrypoint(), to return a non-zero value. 820 821In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 822data access and all interrupt sources masked: 823 824:: 825 826 PSTATE.AIF = 0x7 827 SCTLR.EE = 0 828 829The warm boot entrypoint may be implemented by using TF-A 830``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 831the pre-requisites mentioned in the 832:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 833 834EL3 runtime services framework 835------------------------------ 836 837Software executing in the non-secure state and in the secure state at exception 838levels lower than EL3 will request runtime services using the Secure Monitor 839Call (SMC) instruction. These requests will follow the convention described in 840the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 841identifiers to each SMC request and describes how arguments are passed and 842returned. 843 844The EL3 runtime services framework enables the development of services by 845different providers that can be easily integrated into final product firmware. 846The following sections describe the framework which facilitates the 847registration, initialization and use of runtime services in EL3 Runtime 848Software (BL31). 849 850The design of the runtime services depends heavily on the concepts and 851definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 852Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 853conventions. Please refer to that document for more detailed explanation of 854these terms. 855 856The following runtime services are expected to be implemented first. They have 857not all been instantiated in the current implementation. 858 859#. Standard service calls 860 861 This service is for management of the entire system. The Power State 862 Coordination Interface (`PSCI`_) is the first set of standard service calls 863 defined by Arm (see PSCI section later). 864 865#. Secure-EL1 Payload Dispatcher service 866 867 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 868 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 869 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 870 The Secure Monitor will make these world switches in response to SMCs. The 871 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 872 Application Call OEN ranges. 873 874 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 875 not defined by the `SMCCC`_ or any other standard. As a result, each 876 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 877 service - within TF-A this service is referred to as the Secure-EL1 Payload 878 Dispatcher (SPD). 879 880 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 881 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 882 :ref:`firmware_design_sel1_spd` section below. 883 884#. CPU implementation service 885 886 This service will provide an interface to CPU implementation specific 887 services for a given platform e.g. access to processor errata workarounds. 888 This service is currently unimplemented. 889 890Additional services for Arm Architecture, SiP and OEM calls can be implemented. 891Each implemented service handles a range of SMC function identifiers as 892described in the `SMCCC`_. 893 894Registration 895~~~~~~~~~~~~ 896 897A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 898the name of the service, the range of OENs covered, the type of service and 899initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 900This structure is allocated in a special ELF section ``rt_svc_descs``, enabling 901the framework to find all service descriptors included into BL31. 902 903The specific service for a SMC Function is selected based on the OEN and call 904type of the Function ID, and the framework uses that information in the service 905descriptor to identify the handler for the SMC Call. 906 907The service descriptors do not include information to identify the precise set 908of SMC function identifiers supported by this service implementation, the 909security state from which such calls are valid nor the capability to support 91064-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 911to these aspects of a SMC call is the responsibility of the service 912implementation, the framework is focused on integration of services from 913different providers and minimizing the time taken by the framework before the 914service handler is invoked. 915 916Details of the parameters, requirements and behavior of the initialization and 917call handling functions are provided in the following sections. 918 919Initialization 920~~~~~~~~~~~~~~ 921 922``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 923framework running on the primary CPU during cold boot as part of the BL31 924initialization. This happens prior to initializing a Trusted OS and running 925Normal world boot firmware that might in turn use these services. 926Initialization involves validating each of the declared runtime service 927descriptors, calling the service initialization function and populating the 928index used for runtime lookup of the service. 929 930The BL31 linker script collects all of the declared service descriptors into a 931single array and defines symbols that allow the framework to locate and traverse 932the array, and determine its size. 933 934The framework does basic validation of each descriptor to halt firmware 935initialization if service declaration errors are detected. The framework does 936not check descriptors for the following error conditions, and may behave in an 937unpredictable manner under such scenarios: 938 939#. Overlapping OEN ranges 940#. Multiple descriptors for the same range of OENs and ``call_type`` 941#. Incorrect range of owning entity numbers for a given ``call_type`` 942 943Once validated, the service ``init()`` callback is invoked. This function carries 944out any essential EL3 initialization before servicing requests. The ``init()`` 945function is only invoked on the primary CPU during cold boot. If the service 946uses per-CPU data this must either be initialized for all CPUs during this call, 947or be done lazily when a CPU first issues an SMC call to that service. If 948``init()`` returns anything other than ``0``, this is treated as an initialization 949error and the service is ignored: this does not cause the firmware to halt. 950 951The OEN and call type fields present in the SMC Function ID cover a total of 952128 distinct services, but in practice a single descriptor can cover a range of 953OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 954service handler, the framework uses an array of 128 indices that map every 955distinct OEN/call-type combination either to one of the declared services or to 956indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 957populated for all of the OENs covered by a service after the service ``init()`` 958function has reported success. So a service that fails to initialize will never 959have it's ``handle()`` function invoked. 960 961The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 962Function ID call type and OEN onto a specific service handler in the 963``rt_svc_descs[]`` array. 964 965|Image 1| 966 967.. _handling-an-smc: 968 969Handling an SMC 970~~~~~~~~~~~~~~~ 971 972When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 973Function ID is passed in W0 from the lower exception level (as per the 974`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 975SMC Function which indicates the SMC64 calling convention: such calls are 976ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 977in R0/X0. 978 979Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 980Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 981resulting value might indicate a service that has no handler, in this case the 982framework will also report an Unknown SMC Function ID. Otherwise, the value is 983used as a further index into the ``rt_svc_descs[]`` array to locate the required 984service and handler. 985 986The service's ``handle()`` callback is provided with five of the SMC parameters 987directly, the others are saved into memory for retrieval (if needed) by the 988handler. The handler is also provided with an opaque ``handle`` for use with the 989supporting library for parameter retrieval, setting return values and context 990manipulation; and with ``flags`` indicating the security state of the caller. The 991framework finally sets up the execution stack for the handler, and invokes the 992services ``handle()`` function. 993 994On return from the handler the result registers are populated in X0-X7 as needed 995before restoring the stack and CPU state and returning from the original SMC. 996 997Exception Handling Framework 998---------------------------- 999 1000Please refer to the :ref:`Exception Handling Framework` document. 1001 1002Power State Coordination Interface 1003---------------------------------- 1004 1005TODO: Provide design walkthrough of PSCI implementation. 1006 1007The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 1008mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 1009`Power State Coordination Interface PDD`_ are implemented. The table lists 1010the PSCI v1.1 APIs and their support in generic code. 1011 1012An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 1013requires the platform to export a part of the implementation. Hence the level 1014of support of the mandatory APIs depends upon the support exported by the 1015platform port as well. The Juno and FVP (all variants) platforms export all the 1016required support. 1017 1018+-----------------------------+-------------+-------------------------------+ 1019| PSCI v1.1 API | Supported | Comments | 1020+=============================+=============+===============================+ 1021| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1022+-----------------------------+-------------+-------------------------------+ 1023| ``CPU_SUSPEND`` | Yes\* | | 1024+-----------------------------+-------------+-------------------------------+ 1025| ``CPU_OFF`` | Yes\* | | 1026+-----------------------------+-------------+-------------------------------+ 1027| ``CPU_ON`` | Yes\* | | 1028+-----------------------------+-------------+-------------------------------+ 1029| ``AFFINITY_INFO`` | Yes | | 1030+-----------------------------+-------------+-------------------------------+ 1031| ``MIGRATE`` | Yes\*\* | | 1032+-----------------------------+-------------+-------------------------------+ 1033| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1034+-----------------------------+-------------+-------------------------------+ 1035| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1036+-----------------------------+-------------+-------------------------------+ 1037| ``SYSTEM_OFF`` | Yes\* | | 1038+-----------------------------+-------------+-------------------------------+ 1039| ``SYSTEM_RESET`` | Yes\* | | 1040+-----------------------------+-------------+-------------------------------+ 1041| ``PSCI_FEATURES`` | Yes | | 1042+-----------------------------+-------------+-------------------------------+ 1043| ``CPU_FREEZE`` | No | | 1044+-----------------------------+-------------+-------------------------------+ 1045| ``CPU_DEFAULT_SUSPEND`` | No | | 1046+-----------------------------+-------------+-------------------------------+ 1047| ``NODE_HW_STATE`` | Yes\* | | 1048+-----------------------------+-------------+-------------------------------+ 1049| ``SYSTEM_SUSPEND`` | Yes\* | | 1050+-----------------------------+-------------+-------------------------------+ 1051| ``PSCI_SET_SUSPEND_MODE`` | No | | 1052+-----------------------------+-------------+-------------------------------+ 1053| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1054+-----------------------------+-------------+-------------------------------+ 1055| ``PSCI_STAT_COUNT`` | Yes\* | | 1056+-----------------------------+-------------+-------------------------------+ 1057| ``SYSTEM_RESET2`` | Yes\* | | 1058+-----------------------------+-------------+-------------------------------+ 1059| ``MEM_PROTECT`` | Yes\* | | 1060+-----------------------------+-------------+-------------------------------+ 1061| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1062+-----------------------------+-------------+-------------------------------+ 1063 1064\*Note : These PSCI APIs require platform power management hooks to be 1065registered with the generic PSCI code to be supported. 1066 1067\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1068hooks to be registered with the generic PSCI code to be supported. 1069 1070The PSCI implementation in TF-A is a library which can be integrated with 1071AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1072integrating PSCI library with AArch32 EL3 Runtime Software can be found 1073at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1074 1075.. _firmware_design_sel1_spd: 1076 1077Secure-EL1 Payloads and Dispatchers 1078----------------------------------- 1079 1080On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1081the Trusted OS is coupled with a companion runtime service in the BL31 1082firmware. This service is responsible for the initialisation of the Trusted 1083OS and all communications with it. The Trusted OS is the BL32 stage of the 1084boot flow in TF-A. The firmware will attempt to locate, load and execute a 1085BL32 image. 1086 1087TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1088the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1089 1090TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1091Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1092production system using the Runtime Services Framework. On such a system, the 1093Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1094service. The TF-A build system expects that the dispatcher will define the 1095build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1096as a binary or to compile from source depending on whether the ``BL32`` build 1097option is specified or not. 1098 1099The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1100communication with the normal-world software running in EL1/EL2. Communication 1101is initiated by the normal-world software 1102 1103- either directly through a Fast SMC (as defined in the `SMCCC`_) 1104 1105- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1106 informs the TSPD about the requested power management operation. This allows 1107 the TSP to prepare for or respond to the power state change 1108 1109The TSPD service is responsible for. 1110 1111- Initializing the TSP 1112 1113- Routing requests and responses between the secure and the non-secure 1114 states during the two types of communications just described 1115 1116Initializing a BL32 Image 1117~~~~~~~~~~~~~~~~~~~~~~~~~ 1118 1119The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1120the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1121so. This is provided by: 1122 1123.. code:: c 1124 1125 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1126 1127which returns a reference to the ``entry_point_info`` structure corresponding to 1128the image which will be run in the specified security state. The SPD uses this 1129API to get entry point information for the SECURE image, BL32. 1130 1131In the absence of a BL32 image, BL31 passes control to the normal world 1132bootloader image (BL33). When the BL32 image is present, it is typical 1133that the SPD wants control to be passed to BL32 first and then later to BL33. 1134 1135To do this the SPD has to register a BL32 initialization function during 1136initialization of the SPD service. The BL32 initialization function has this 1137prototype: 1138 1139.. code:: c 1140 1141 int32_t init(void); 1142 1143and is registered using the ``bl31_register_bl32_init()`` function. 1144 1145TF-A supports two approaches for the SPD to pass control to BL32 before 1146returning through EL3 and running the non-trusted firmware (BL33): 1147 1148#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1149 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1150 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1151 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1152 1153 When the BL32 has completed initialization at Secure-EL1, it returns to 1154 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1155 receipt of this SMC, the SPD service handler should switch the CPU context 1156 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1157 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1158 the normal world firmware BL33. On return from the handler the framework 1159 will exit to EL2 and run BL33. 1160 1161#. The BL32 setup function registers an initialization function using 1162 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1163 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1164 entrypoint. 1165 1166 .. note:: 1167 The Test SPD service included with TF-A provides one implementation 1168 of such a mechanism. 1169 1170 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1171 SPD service handler invokes the synchronous call return mechanism to return 1172 to the BL32 initialization function. On return from this function, 1173 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1174 continue the boot process in the normal world. 1175 1176Crash Reporting in BL31 1177----------------------- 1178 1179BL31 implements a scheme for reporting the processor state when an unhandled 1180exception is encountered. The reporting mechanism attempts to preserve all the 1181register contents and report it via a dedicated UART (PL011 console). BL31 1182reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1183 1184A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1185the per-CPU pointer cache. The implementation attempts to minimise the memory 1186required for this feature. The file ``crash_reporting.S`` contains the 1187implementation for crash reporting. 1188 1189The sample crash output is shown below. 1190 1191:: 1192 1193 x0 = 0x000000002a4a0000 1194 x1 = 0x0000000000000001 1195 x2 = 0x0000000000000002 1196 x3 = 0x0000000000000003 1197 x4 = 0x0000000000000004 1198 x5 = 0x0000000000000005 1199 x6 = 0x0000000000000006 1200 x7 = 0x0000000000000007 1201 x8 = 0x0000000000000008 1202 x9 = 0x0000000000000009 1203 x10 = 0x0000000000000010 1204 x11 = 0x0000000000000011 1205 x12 = 0x0000000000000012 1206 x13 = 0x0000000000000013 1207 x14 = 0x0000000000000014 1208 x15 = 0x0000000000000015 1209 x16 = 0x0000000000000016 1210 x17 = 0x0000000000000017 1211 x18 = 0x0000000000000018 1212 x19 = 0x0000000000000019 1213 x20 = 0x0000000000000020 1214 x21 = 0x0000000000000021 1215 x22 = 0x0000000000000022 1216 x23 = 0x0000000000000023 1217 x24 = 0x0000000000000024 1218 x25 = 0x0000000000000025 1219 x26 = 0x0000000000000026 1220 x27 = 0x0000000000000027 1221 x28 = 0x0000000000000028 1222 x29 = 0x0000000000000029 1223 x30 = 0x0000000088000b78 1224 scr_el3 = 0x000000000003073d 1225 sctlr_el3 = 0x00000000b0cd183f 1226 cptr_el3 = 0x0000000000000000 1227 tcr_el3 = 0x000000008080351c 1228 daif = 0x00000000000002c0 1229 mair_el3 = 0x00000000004404ff 1230 spsr_el3 = 0x0000000060000349 1231 elr_el3 = 0x0000000088000114 1232 ttbr0_el3 = 0x0000000004018201 1233 esr_el3 = 0x00000000be000000 1234 far_el3 = 0x0000000000000000 1235 spsr_el1 = 0x0000000000000000 1236 elr_el1 = 0x0000000000000000 1237 spsr_abt = 0x0000000000000000 1238 spsr_und = 0x0000000000000000 1239 spsr_irq = 0x0000000000000000 1240 spsr_fiq = 0x0000000000000000 1241 sctlr_el1 = 0x0000000030d00800 1242 actlr_el1 = 0x0000000000000000 1243 cpacr_el1 = 0x0000000000000000 1244 csselr_el1 = 0x0000000000000000 1245 sp_el1 = 0x0000000000000000 1246 esr_el1 = 0x0000000000000000 1247 ttbr0_el1 = 0x0000000000000000 1248 ttbr1_el1 = 0x0000000000000000 1249 mair_el1 = 0x0000000000000000 1250 amair_el1 = 0x0000000000000000 1251 tcr_el1 = 0x0000000000000000 1252 tpidr_el1 = 0x0000000000000000 1253 tpidr_el0 = 0x0000000000000000 1254 tpidrro_el0 = 0x0000000000000000 1255 par_el1 = 0x0000000000000000 1256 mpidr_el1 = 0x0000000080000000 1257 afsr0_el1 = 0x0000000000000000 1258 afsr1_el1 = 0x0000000000000000 1259 contextidr_el1 = 0x0000000000000000 1260 vbar_el1 = 0x0000000000000000 1261 cntp_ctl_el0 = 0x0000000000000000 1262 cntp_cval_el0 = 0x0000000000000000 1263 cntv_ctl_el0 = 0x0000000000000000 1264 cntv_cval_el0 = 0x0000000000000000 1265 cntkctl_el1 = 0x0000000000000000 1266 sp_el0 = 0x0000000004014940 1267 isr_el1 = 0x0000000000000000 1268 dacr32_el2 = 0x0000000000000000 1269 ifsr32_el2 = 0x0000000000000000 1270 icc_hppir0_el1 = 0x00000000000003ff 1271 icc_hppir1_el1 = 0x00000000000003ff 1272 icc_ctlr_el3 = 0x0000000000080400 1273 gicd_ispendr regs (Offsets 0x200-0x278) 1274 Offset Value 1275 0x200: 0x0000000000000000 1276 0x208: 0x0000000000000000 1277 0x210: 0x0000000000000000 1278 0x218: 0x0000000000000000 1279 0x220: 0x0000000000000000 1280 0x228: 0x0000000000000000 1281 0x230: 0x0000000000000000 1282 0x238: 0x0000000000000000 1283 0x240: 0x0000000000000000 1284 0x248: 0x0000000000000000 1285 0x250: 0x0000000000000000 1286 0x258: 0x0000000000000000 1287 0x260: 0x0000000000000000 1288 0x268: 0x0000000000000000 1289 0x270: 0x0000000000000000 1290 0x278: 0x0000000000000000 1291 1292Guidelines for Reset Handlers 1293----------------------------- 1294 1295TF-A implements a framework that allows CPU and platform ports to perform 1296actions very early after a CPU is released from reset in both the cold and warm 1297boot paths. This is done by calling the ``reset_handler()`` function in both 1298the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1299handling functions. 1300 1301Details for implementing a CPU specific reset handler can be found in 1302Section 8. Details for implementing a platform specific reset handler can be 1303found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). 1304 1305When adding functionality to a reset handler, keep in mind that if a different 1306reset handling behavior is required between the first and the subsequent 1307invocations of the reset handling code, this should be detected at runtime. 1308In other words, the reset handler should be able to detect whether an action has 1309already been performed and act as appropriate. Possible courses of actions are, 1310e.g. skip the action the second time, or undo/redo it. 1311 1312.. _configuring-secure-interrupts: 1313 1314Configuring secure interrupts 1315----------------------------- 1316 1317The GIC driver is responsible for performing initial configuration of secure 1318interrupts on the platform. To this end, the platform is expected to provide the 1319GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1320interrupt configuration during the driver initialisation. 1321 1322Secure interrupt configuration are specified in an array of secure interrupt 1323properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1324``interrupt_props`` member points to an array of interrupt properties. Each 1325element of the array specifies the interrupt number and its attributes 1326(priority, group, configuration). Each element of the array shall be populated 1327by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1328 1329- 10-bit interrupt number, 1330 1331- 8-bit interrupt priority, 1332 1333- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1334 ``INTR_TYPE_NS``), 1335 1336- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1337 ``GIC_INTR_CFG_EDGE``). 1338 1339.. _firmware_design_cpu_ops_fwk: 1340 1341CPU specific operations framework 1342--------------------------------- 1343 1344Certain aspects of the Armv8-A architecture are implementation defined, 1345that is, certain behaviours are not architecturally defined, but must be 1346defined and documented by individual processor implementations. TF-A 1347implements a framework which categorises the common implementation defined 1348behaviours and allows a processor to export its implementation of that 1349behaviour. The categories are: 1350 1351#. Processor specific reset sequence. 1352 1353#. Processor specific power down sequences. 1354 1355#. Processor specific register dumping as a part of crash reporting. 1356 1357#. Errata status reporting. 1358 1359Each of the above categories fulfils a different requirement. 1360 1361#. allows any processor specific initialization before the caches and MMU 1362 are turned on, like implementation of errata workarounds, entry into 1363 the intra-cluster coherency domain etc. 1364 1365#. allows each processor to implement the power down sequence mandated in 1366 its Technical Reference Manual (TRM). 1367 1368#. allows a processor to provide additional information to the developer 1369 in the event of a crash, for example Cortex-A53 has registers which 1370 can expose the data cache contents. 1371 1372#. allows a processor to define a function that inspects and reports the status 1373 of all errata workarounds on that processor. 1374 1375Please note that only 2. is mandated by the TRM. 1376 1377The CPU specific operations framework scales to accommodate a large number of 1378different CPUs during power down and reset handling. The platform can specify 1379any CPU optimization it wants to enable for each CPU. It can also specify 1380the CPU errata workarounds to be applied for each CPU type during reset 1381handling by defining CPU errata compile time macros. Details on these macros 1382can be found in the :ref:`Arm CPU Specific Build Macros` document. 1383 1384The CPU specific operations framework depends on the ``cpu_ops`` structure which 1385needs to be exported for each type of CPU in the platform. It is defined in 1386``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1387``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1388``cpu_reg_dump()``. 1389 1390The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1391suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1392exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1393configuration, these CPU specific files must be included in the build by 1394the platform makefile. The generic CPU specific operations framework code exists 1395in ``lib/cpus/aarch64/cpu_helpers.S``. 1396 1397CPU specific Reset Handling 1398~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1399 1400After a reset, the state of the CPU when it calls generic reset handler is: 1401MMU turned off, both instruction and data caches turned off and not part 1402of any coherency domain. 1403 1404The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1405the platform to perform any system initialization required and any system 1406errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1407the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1408array and returns it. Note that only the part number and implementer fields 1409in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1410the returned ``cpu_ops`` is then invoked which executes the required reset 1411handling for that CPU and also any errata workarounds enabled by the platform. 1412This function must preserve the values of general purpose registers x20 to x29. 1413 1414Refer to Section "Guidelines for Reset Handlers" for general guidelines 1415regarding placement of code in a reset handler. 1416 1417CPU specific power down sequence 1418~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1419 1420During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1421entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1422retrieved during power down sequences. 1423 1424Various CPU drivers register handlers to perform power down at certain power 1425levels for that specific CPU. The PSCI service, upon receiving a power down 1426request, determines the highest power level at which to execute power down 1427sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1428pick the right power down handler for the requested level. The function 1429retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1430retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1431requested power level is higher than what a CPU driver supports, the handler 1432registered for highest level is invoked. 1433 1434At runtime the platform hooks for power down are invoked by the PSCI service to 1435perform platform specific operations during a power down sequence, for example 1436turning off CCI coherency during a cluster power down. 1437 1438CPU specific register reporting during crash 1439~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1440 1441If the crash reporting is enabled in BL31, when a crash occurs, the crash 1442reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1443``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1444``cpu_ops`` is invoked, which then returns the CPU specific register values to 1445be reported and a pointer to the ASCII list of register names in a format 1446expected by the crash reporting framework. 1447 1448.. _firmware_design_cpu_errata_reporting: 1449 1450CPU errata status reporting 1451~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1452 1453Errata workarounds for CPUs supported in TF-A are applied during both cold and 1454warm boots, shortly after reset. Individual Errata workarounds are enabled as 1455build options. Some errata workarounds have potential run-time implications; 1456therefore some are enabled by default, others not. Platform ports shall 1457override build options to enable or disable errata as appropriate. The CPU 1458drivers take care of applying errata workarounds that are enabled and applicable 1459to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more 1460information. 1461 1462Functions in CPU drivers that apply errata workaround must follow the 1463conventions listed below. 1464 1465The errata workaround must be authored as two separate functions: 1466 1467- One that checks for errata. This function must determine whether that errata 1468 applies to the current CPU. Typically this involves matching the current 1469 CPUs revision and variant against a value that's known to be affected by the 1470 errata. If the function determines that the errata applies to this CPU, it 1471 must return ``ERRATA_APPLIES``; otherwise, it must return 1472 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1473 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1474 1475For an errata identified as ``E``, the check function must be named 1476``check_errata_E``. 1477 1478This function will be invoked at different times, both from assembly and from 1479C run time. Therefore it must follow AAPCS, and must not use stack. 1480 1481- Another one that applies the errata workaround. This function would call the 1482 check function described above, and applies errata workaround if required. 1483 1484CPU drivers that apply errata workaround can optionally implement an assembly 1485function that report the status of errata workarounds pertaining to that CPU. 1486For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1487macro, the errata reporting function, if it exists, must be named 1488``cpux_errata_report``. This function will always be called with MMU enabled; it 1489must follow AAPCS and may use stack. 1490 1491In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1492runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1493status reporting function, if one exists, for that type of CPU. 1494 1495To report the status of each errata workaround, the function shall use the 1496assembler macro ``report_errata``, passing it: 1497 1498- The build option that enables the errata; 1499 1500- The name of the CPU: this must be the same identifier that CPU driver 1501 registered itself with, using ``declare_cpu_ops``; 1502 1503- And the errata identifier: the identifier must match what's used in the 1504 errata's check function described above. 1505 1506The errata status reporting function will be called once per CPU type/errata 1507combination during the software's active life time. 1508 1509It's expected that whenever an errata workaround is submitted to TF-A, the 1510errata reporting function is appropriately extended to report its status as 1511well. 1512 1513Reporting the status of errata workaround is for informational purpose only; it 1514has no functional significance. 1515 1516Memory layout of BL images 1517-------------------------- 1518 1519Each bootloader image can be divided in 2 parts: 1520 1521- the static contents of the image. These are data actually stored in the 1522 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1523 sections; 1524 1525- the run-time contents of the image. These are data that don't occupy any 1526 space in the binary on the disk. The ELF binary just contains some 1527 metadata indicating where these data will be stored at run-time and the 1528 corresponding sections need to be allocated and initialized at run-time. 1529 In the ELF terminology, they are called ``NOBITS`` sections. 1530 1531All PROGBITS sections are grouped together at the beginning of the image, 1532followed by all NOBITS sections. This is true for all TF-A images and it is 1533governed by the linker scripts. This ensures that the raw binary images are 1534as small as possible. If a NOBITS section was inserted in between PROGBITS 1535sections then the resulting binary file would contain zero bytes in place of 1536this NOBITS section, making the image unnecessarily bigger. Smaller images 1537allow faster loading from the FIP to the main memory. 1538 1539For BL31, a platform can specify an alternate location for NOBITS sections 1540(other than immediately following PROGBITS sections) by setting 1541``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1542``BL31_NOBITS_LIMIT``. 1543 1544Linker scripts and symbols 1545~~~~~~~~~~~~~~~~~~~~~~~~~~ 1546 1547Each bootloader stage image layout is described by its own linker script. The 1548linker scripts export some symbols into the program symbol table. Their values 1549correspond to particular addresses. TF-A code can refer to these symbols to 1550figure out the image memory layout. 1551 1552Linker symbols follow the following naming convention in TF-A. 1553 1554- ``__<SECTION>_START__`` 1555 1556 Start address of a given section named ``<SECTION>``. 1557 1558- ``__<SECTION>_END__`` 1559 1560 End address of a given section named ``<SECTION>``. If there is an alignment 1561 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1562 to the end address of the section's actual contents, rounded up to the right 1563 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1564 actual end address of the section's contents. 1565 1566- ``__<SECTION>_UNALIGNED_END__`` 1567 1568 End address of a given section named ``<SECTION>`` without any padding or 1569 rounding up due to some alignment constraint. 1570 1571- ``__<SECTION>_SIZE__`` 1572 1573 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1574 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1575 corresponds to the size of the section's actual contents, rounded up to the 1576 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1577 to know the actual size of the section's contents. 1578 1579- ``__<SECTION>_UNALIGNED_SIZE__`` 1580 1581 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1582 rounding up due to some alignment constraint. In other words, 1583 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1584 1585Some of the linker symbols are mandatory as TF-A code relies on them to be 1586defined. They are listed in the following subsections. Some of them must be 1587provided for each bootloader stage and some are specific to a given bootloader 1588stage. 1589 1590The linker scripts define some extra, optional symbols. They are not actually 1591used by any code but they help in understanding the bootloader images' memory 1592layout as they are easy to spot in the link map files. 1593 1594Common linker symbols 1595^^^^^^^^^^^^^^^^^^^^^ 1596 1597All BL images share the following requirements: 1598 1599- The BSS section must be zero-initialised before executing any C code. 1600- The coherent memory section (if enabled) must be zero-initialised as well. 1601- The MMU setup code needs to know the extents of the coherent and read-only 1602 memory regions to set the right memory attributes. When 1603 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1604 read-only memory region is divided between code and data. 1605 1606The following linker symbols are defined for this purpose: 1607 1608- ``__BSS_START__`` 1609- ``__BSS_SIZE__`` 1610- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1611- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1612- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1613- ``__RO_START__`` 1614- ``__RO_END__`` 1615- ``__TEXT_START__`` 1616- ``__TEXT_END__`` 1617- ``__RODATA_START__`` 1618- ``__RODATA_END__`` 1619 1620BL1's linker symbols 1621^^^^^^^^^^^^^^^^^^^^ 1622 1623BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1624it is entirely executed in place but it needs some read-write memory for its 1625mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1626relocated from ROM to RAM before executing any C code. 1627 1628The following additional linker symbols are defined for BL1: 1629 1630- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1631 and ``.data`` section in ROM. 1632- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1633 aligned on a 16-byte boundary. 1634- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1635 copied over. Must be aligned on a 16-byte boundary. 1636- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1637- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1638- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1639 1640How to choose the right base addresses for each bootloader stage image 1641~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1642 1643There is currently no support for dynamic image loading in TF-A. This means 1644that all bootloader images need to be linked against their ultimate runtime 1645locations and the base addresses of each image must be chosen carefully such 1646that images don't overlap each other in an undesired way. As the code grows, 1647the base addresses might need adjustments to cope with the new memory layout. 1648 1649The memory layout is completely specific to the platform and so there is no 1650general recipe for choosing the right base addresses for each bootloader image. 1651However, there are tools to aid in understanding the memory layout. These are 1652the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1653being the stage bootloader. They provide a detailed view of the memory usage of 1654each image. Among other useful information, they provide the end address of 1655each image. 1656 1657- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1658- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1659- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1660- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1661 1662For each bootloader image, the platform code must provide its start address 1663as well as a limit address that it must not overstep. The latter is used in the 1664linker scripts to check that the image doesn't grow past that address. If that 1665happens, the linker will issue a message similar to the following: 1666 1667:: 1668 1669 aarch64-none-elf-ld: BLx has exceeded its limit. 1670 1671Additionally, if the platform memory layout implies some image overlaying like 1672on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1673sections must not overstep. The platform code must provide those. 1674 1675TF-A does not provide any mechanism to verify at boot time that the memory 1676to load a new image is free to prevent overwriting a previously loaded image. 1677The platform must specify the memory available in the system for all the 1678relevant BL images to be loaded. 1679 1680For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1681return the region defined by the platform where BL1 intends to load BL2. The 1682``load_image()`` function performs bounds check for the image size based on the 1683base and maximum image size provided by the platforms. Platforms must take 1684this behaviour into account when defining the base/size for each of the images. 1685 1686Memory layout on Arm development platforms 1687^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1688 1689The following list describes the memory layout on the Arm development platforms: 1690 1691- A 4KB page of shared memory is used for communication between Trusted 1692 Firmware and the platform's power controller. This is located at the base of 1693 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1694 images is reduced by the size of the shared memory. 1695 1696 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1697 this is also used for the MHU payload when passing messages to and from the 1698 SCP. 1699 1700- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1701 and also the dynamic firmware configurations. 1702 1703- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1704 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1705 data are relocated to the top of Trusted SRAM at runtime. 1706 1707- BL2 is loaded below BL1 RW 1708 1709- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1710 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1711 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1712 remain valid only until execution reaches the EL3 Runtime Software entry 1713 point during a cold boot. 1714 1715- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1716 region and transferred to the SCP before being overwritten by EL3 Runtime 1717 Software. 1718 1719- BL32 (for AArch64) can be loaded in one of the following locations: 1720 1721 - Trusted SRAM 1722 - Trusted DRAM (FVP only) 1723 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1724 controller) 1725 1726 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1727 BL31. 1728 1729The location of the BL32 image will result in different memory maps. This is 1730illustrated for both FVP and Juno in the following diagrams, using the TSP as 1731an example. 1732 1733.. note:: 1734 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1735 layout of the other images in Trusted SRAM. 1736 1737CONFIG section in memory layouts shown below contains: 1738 1739:: 1740 1741 +--------------------+ 1742 |bl2_mem_params_descs| 1743 |--------------------| 1744 | fw_configs | 1745 +--------------------+ 1746 1747``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1748BL image during boot. 1749 1750``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1751 1752**FVP with TSP in Trusted SRAM with firmware configs :** 1753(These diagrams only cover the AArch64 case) 1754 1755:: 1756 1757 DRAM 1758 0xffffffff +----------+ 1759 : : 1760 |----------| 1761 |HW_CONFIG | 1762 0x83000000 |----------| (non-secure) 1763 | | 1764 0x80000000 +----------+ 1765 1766 Trusted SRAM 1767 0x04040000 +----------+ loaded by BL2 +----------------+ 1768 | BL1 (rw) | <<<<<<<<<<<<< | | 1769 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1770 | BL2 | <<<<<<<<<<<<< | | 1771 |----------| <<<<<<<<<<<<< |----------------| 1772 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1773 | | <<<<<<<<<<<<< |----------------| 1774 | | <<<<<<<<<<<<< | BL32 | 1775 0x04003000 +----------+ +----------------+ 1776 | CONFIG | 1777 0x04001000 +----------+ 1778 | Shared | 1779 0x04000000 +----------+ 1780 1781 Trusted ROM 1782 0x04000000 +----------+ 1783 | BL1 (ro) | 1784 0x00000000 +----------+ 1785 1786**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1787 1788:: 1789 1790 DRAM 1791 0xffffffff +--------------+ 1792 : : 1793 |--------------| 1794 | HW_CONFIG | 1795 0x83000000 |--------------| (non-secure) 1796 | | 1797 0x80000000 +--------------+ 1798 1799 Trusted DRAM 1800 0x08000000 +--------------+ 1801 | BL32 | 1802 0x06000000 +--------------+ 1803 1804 Trusted SRAM 1805 0x04040000 +--------------+ loaded by BL2 +----------------+ 1806 | BL1 (rw) | <<<<<<<<<<<<< | | 1807 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1808 | BL2 | <<<<<<<<<<<<< | | 1809 |--------------| <<<<<<<<<<<<< |----------------| 1810 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1811 | | +----------------+ 1812 0x04003000 +--------------+ 1813 | CONFIG | 1814 0x04001000 +--------------+ 1815 | Shared | 1816 0x04000000 +--------------+ 1817 1818 Trusted ROM 1819 0x04000000 +--------------+ 1820 | BL1 (ro) | 1821 0x00000000 +--------------+ 1822 1823**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1824 1825:: 1826 1827 DRAM 1828 0xffffffff +----------+ 1829 | BL32 | (secure) 1830 0xff000000 +----------+ 1831 | | 1832 |----------| 1833 |HW_CONFIG | 1834 0x83000000 |----------| (non-secure) 1835 | | 1836 0x80000000 +----------+ 1837 1838 Trusted SRAM 1839 0x04040000 +----------+ loaded by BL2 +----------------+ 1840 | BL1 (rw) | <<<<<<<<<<<<< | | 1841 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1842 | BL2 | <<<<<<<<<<<<< | | 1843 |----------| <<<<<<<<<<<<< |----------------| 1844 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1845 | | +----------------+ 1846 0x04003000 +----------+ 1847 | CONFIG | 1848 0x04001000 +----------+ 1849 | Shared | 1850 0x04000000 +----------+ 1851 1852 Trusted ROM 1853 0x04000000 +----------+ 1854 | BL1 (ro) | 1855 0x00000000 +----------+ 1856 1857**Juno with BL32 in Trusted SRAM :** 1858 1859:: 1860 1861 Flash0 1862 0x0C000000 +----------+ 1863 : : 1864 0x0BED0000 |----------| 1865 | BL1 (ro) | 1866 0x0BEC0000 |----------| 1867 : : 1868 0x08000000 +----------+ BL31 is loaded 1869 after SCP_BL2 has 1870 Trusted SRAM been sent to SCP 1871 0x04040000 +----------+ loaded by BL2 +----------------+ 1872 | BL1 (rw) | <<<<<<<<<<<<< | | 1873 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1874 | BL2 | <<<<<<<<<<<<< | | 1875 |----------| <<<<<<<<<<<<< |----------------| 1876 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1877 | | <<<<<<<<<<<<< |----------------| 1878 | | <<<<<<<<<<<<< | BL32 | 1879 | | +----------------+ 1880 | | 1881 0x04001000 +----------+ 1882 | MHU | 1883 0x04000000 +----------+ 1884 1885**Juno with BL32 in TZC-secured DRAM :** 1886 1887:: 1888 1889 DRAM 1890 0xFFE00000 +----------+ 1891 | BL32 | (secure) 1892 0xFF000000 |----------| 1893 | | 1894 : : (non-secure) 1895 | | 1896 0x80000000 +----------+ 1897 1898 Flash0 1899 0x0C000000 +----------+ 1900 : : 1901 0x0BED0000 |----------| 1902 | BL1 (ro) | 1903 0x0BEC0000 |----------| 1904 : : 1905 0x08000000 +----------+ BL31 is loaded 1906 after SCP_BL2 has 1907 Trusted SRAM been sent to SCP 1908 0x04040000 +----------+ loaded by BL2 +----------------+ 1909 | BL1 (rw) | <<<<<<<<<<<<< | | 1910 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1911 | BL2 | <<<<<<<<<<<<< | | 1912 |----------| <<<<<<<<<<<<< |----------------| 1913 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1914 | | +----------------+ 1915 0x04001000 +----------+ 1916 | MHU | 1917 0x04000000 +----------+ 1918 1919.. _firmware_design_fip: 1920 1921Firmware Image Package (FIP) 1922---------------------------- 1923 1924Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1925potentially other payloads) into a single archive that can be loaded by TF-A 1926from non-volatile platform storage. A driver to load images from a FIP has 1927been added to the storage layer and allows a package to be read from supported 1928platform storage. A tool to create Firmware Image Packages is also provided 1929and described below. 1930 1931Firmware Image Package layout 1932~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1933 1934The FIP layout consists of a table of contents (ToC) followed by payload data. 1935The ToC itself has a header followed by one or more table entries. The ToC is 1936terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1937the offset equals the total size of the FIP file. All ToC entries describe some 1938payload data that has been appended to the end of the binary package. With the 1939information provided in the ToC entry the corresponding payload data can be 1940retrieved. 1941 1942:: 1943 1944 ------------------ 1945 | ToC Header | 1946 |----------------| 1947 | ToC Entry 0 | 1948 |----------------| 1949 | ToC Entry 1 | 1950 |----------------| 1951 | ToC End Marker | 1952 |----------------| 1953 | | 1954 | Data 0 | 1955 | | 1956 |----------------| 1957 | | 1958 | Data 1 | 1959 | | 1960 ------------------ 1961 1962The ToC header and entry formats are described in the header file 1963``include/tools_share/firmware_image_package.h``. This file is used by both the 1964tool and TF-A. 1965 1966The ToC header has the following fields: 1967 1968:: 1969 1970 `name`: The name of the ToC. This is currently used to validate the header. 1971 `serial_number`: A non-zero number provided by the creation tool 1972 `flags`: Flags associated with this data. 1973 Bits 0-31: Reserved 1974 Bits 32-47: Platform defined 1975 Bits 48-63: Reserved 1976 1977A ToC entry has the following fields: 1978 1979:: 1980 1981 `uuid`: All files are referred to by a pre-defined Universally Unique 1982 IDentifier [UUID] . The UUIDs are defined in 1983 `include/tools_share/firmware_image_package.h`. The platform translates 1984 the requested image name into the corresponding UUID when accessing the 1985 package. 1986 `offset_address`: The offset address at which the corresponding payload data 1987 can be found. The offset is calculated from the ToC base address. 1988 `size`: The size of the corresponding payload data in bytes. 1989 `flags`: Flags associated with this entry. None are yet defined. 1990 1991Firmware Image Package creation tool 1992~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1993 1994The FIP creation tool can be used to pack specified images into a binary 1995package that can be loaded by TF-A from platform storage. The tool currently 1996only supports packing bootloader images. Additional image definitions can be 1997added to the tool as required. 1998 1999The tool can be found in ``tools/fiptool``. 2000 2001Loading from a Firmware Image Package (FIP) 2002~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2003 2004The Firmware Image Package (FIP) driver can load images from a binary package on 2005non-volatile platform storage. For the Arm development platforms, this is 2006currently NOR FLASH. 2007 2008Bootloader images are loaded according to the platform policy as specified by 2009the function ``plat_get_image_source()``. For the Arm development platforms, this 2010means the platform will attempt to load images from a Firmware Image Package 2011located at the start of NOR FLASH0. 2012 2013The Arm development platforms' policy is to only allow loading of a known set of 2014images. The platform policy can be modified to allow additional images. 2015 2016Use of coherent memory in TF-A 2017------------------------------ 2018 2019There might be loss of coherency when physical memory with mismatched 2020shareability, cacheability and memory attributes is accessed by multiple CPUs 2021(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2022in TF-A during power up/down sequences when coherency, MMU and caches are 2023turned on/off incrementally. 2024 2025TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2026in the translation tables. The translation granule size in TF-A is 4KB. This 2027is the smallest possible size of the coherent memory region. 2028 2029By default, all data structures which are susceptible to accesses with 2030mismatched attributes from various CPUs are allocated in a coherent memory 2031region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2032region accesses are Outer Shareable, non-cacheable and they can be accessed with 2033the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2034at least an extra page of memory, TF-A is able to work around coherency issues 2035due to mismatched memory attributes. 2036 2037The alternative to the above approach is to allocate the susceptible data 2038structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2039approach requires the data structures to be designed so that it is possible to 2040work around the issue of mismatched memory attributes by performing software 2041cache maintenance on them. 2042 2043Disabling the use of coherent memory in TF-A 2044~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2045 2046It might be desirable to avoid the cost of allocating coherent memory on 2047platforms which are memory constrained. TF-A enables inclusion of coherent 2048memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2049This flag is enabled by default. It can be disabled to choose the second 2050approach described above. 2051 2052The below sections analyze the data structures allocated in the coherent memory 2053region and the changes required to allocate them in normal memory. 2054 2055Coherent memory usage in PSCI implementation 2056~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2057 2058The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2059tree information for state management of power domains. By default, this data 2060structure is allocated in the coherent memory region in TF-A because it can be 2061accessed by multiple CPUs, either with caches enabled or disabled. 2062 2063.. code:: c 2064 2065 typedef struct non_cpu_pwr_domain_node { 2066 /* 2067 * Index of the first CPU power domain node level 0 which has this node 2068 * as its parent. 2069 */ 2070 unsigned int cpu_start_idx; 2071 2072 /* 2073 * Number of CPU power domains which are siblings of the domain indexed 2074 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2075 * -> cpu_start_idx + ncpus' have this node as their parent. 2076 */ 2077 unsigned int ncpus; 2078 2079 /* 2080 * Index of the parent power domain node. 2081 */ 2082 unsigned int parent_node; 2083 2084 plat_local_state_t local_state; 2085 2086 unsigned char level; 2087 2088 /* For indexing the psci_lock array*/ 2089 unsigned char lock_index; 2090 } non_cpu_pd_node_t; 2091 2092In order to move this data structure to normal memory, the use of each of its 2093fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2094``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2095them from coherent memory involves only doing a clean and invalidate of the 2096cache lines after these fields are written. 2097 2098The field ``local_state`` can be concurrently accessed by multiple CPUs in 2099different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2100mutual exclusion to this field and a clean and invalidate is needed after it 2101is written. 2102 2103Bakery lock data 2104~~~~~~~~~~~~~~~~ 2105 2106The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2107and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2108defined as follows: 2109 2110.. code:: c 2111 2112 typedef struct bakery_lock { 2113 /* 2114 * The lock_data is a bit-field of 2 members: 2115 * Bit[0] : choosing. This field is set when the CPU is 2116 * choosing its bakery number. 2117 * Bits[1 - 15] : number. This is the bakery number allocated. 2118 */ 2119 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2120 } bakery_lock_t; 2121 2122It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2123fields can be read by all CPUs but only written to by the owning CPU. 2124 2125Depending upon the data cache line size, the per-CPU fields of the 2126``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2127These per-CPU fields can be read and written during lock contention by multiple 2128CPUs with mismatched memory attributes. Since these fields are a part of the 2129lock implementation, they do not have access to any other locking primitive to 2130safeguard against the resulting coherency issues. As a result, simple software 2131cache maintenance is not enough to allocate them in coherent memory. Consider 2132the following example. 2133 2134CPU0 updates its per-CPU field with data cache enabled. This write updates a 2135local cache line which contains a copy of the fields for other CPUs as well. Now 2136CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2137disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2138its field in any other cache line in the system. This operation will invalidate 2139the update made by CPU0 as well. 2140 2141To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2142has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2143algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2144for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2145needed for a CPU into a section ``bakery_lock``. The linker allocates the memory 2146for other cores by using the total size allocated for the bakery_lock section 2147and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2148perform software cache maintenance on the lock data structure without running 2149into coherency issues associated with mismatched attributes. 2150 2151The bakery lock data structure ``bakery_info_t`` is defined for use when 2152``USE_COHERENT_MEM`` is disabled as follows: 2153 2154.. code:: c 2155 2156 typedef struct bakery_info { 2157 /* 2158 * The lock_data is a bit-field of 2 members: 2159 * Bit[0] : choosing. This field is set when the CPU is 2160 * choosing its bakery number. 2161 * Bits[1 - 15] : number. This is the bakery number allocated. 2162 */ 2163 volatile uint16_t lock_data; 2164 } bakery_info_t; 2165 2166The ``bakery_info_t`` represents a single per-CPU field of one lock and 2167the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2168system represents the complete bakery lock. The view in memory for a system 2169with n bakery locks are: 2170 2171:: 2172 2173 bakery_lock section start 2174 |----------------| 2175 | `bakery_info_t`| <-- Lock_0 per-CPU field 2176 | Lock_0 | for CPU0 2177 |----------------| 2178 | `bakery_info_t`| <-- Lock_1 per-CPU field 2179 | Lock_1 | for CPU0 2180 |----------------| 2181 | .... | 2182 |----------------| 2183 | `bakery_info_t`| <-- Lock_N per-CPU field 2184 | Lock_N | for CPU0 2185 ------------------ 2186 | XXXXX | 2187 | Padding to | 2188 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2189 | Granule | continuous memory for remaining CPUs. 2190 ------------------ 2191 | `bakery_info_t`| <-- Lock_0 per-CPU field 2192 | Lock_0 | for CPU1 2193 |----------------| 2194 | `bakery_info_t`| <-- Lock_1 per-CPU field 2195 | Lock_1 | for CPU1 2196 |----------------| 2197 | .... | 2198 |----------------| 2199 | `bakery_info_t`| <-- Lock_N per-CPU field 2200 | Lock_N | for CPU1 2201 ------------------ 2202 | XXXXX | 2203 | Padding to | 2204 | next Cache WB | 2205 | Granule | 2206 ------------------ 2207 2208Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2209operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2210``bakery_lock`` section need to be fetched and appropriate cache operations need 2211to be performed for each access. 2212 2213On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2214driver (``arm_lock``). 2215 2216Non Functional Impact of removing coherent memory 2217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2218 2219Removal of the coherent memory region leads to the additional software overhead 2220of performing cache maintenance for the affected data structures. However, since 2221the memory where the data structures are allocated is cacheable, the overhead is 2222mostly mitigated by an increase in performance. 2223 2224There is however a performance impact for bakery locks, due to: 2225 2226- Additional cache maintenance operations, and 2227- Multiple cache line reads for each lock operation, since the bakery locks 2228 for each CPU are distributed across different cache lines. 2229 2230The implementation has been optimized to minimize this additional overhead. 2231Measurements indicate that when bakery locks are allocated in Normal memory, the 2232minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2233in Device memory the same is 2 micro seconds. The measurements were done on the 2234Juno Arm development platform. 2235 2236As mentioned earlier, almost a page of memory can be saved by disabling 2237``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2238whether coherent memory should be used. If a platform disables 2239``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2240optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2241:ref:`Porting Guide`). Refer to the reference platform code for examples. 2242 2243Isolating code and read-only data on separate memory pages 2244---------------------------------------------------------- 2245 2246In the Armv8-A VMSA, translation table entries include fields that define the 2247properties of the target memory region, such as its access permissions. The 2248smallest unit of memory that can be addressed by a translation table entry is 2249a memory page. Therefore, if software needs to set different permissions on two 2250memory regions then it needs to map them using different memory pages. 2251 2252The default memory layout for each BL image is as follows: 2253 2254:: 2255 2256 | ... | 2257 +-------------------+ 2258 | Read-write data | 2259 +-------------------+ Page boundary 2260 | <Padding> | 2261 +-------------------+ 2262 | Exception vectors | 2263 +-------------------+ 2 KB boundary 2264 | <Padding> | 2265 +-------------------+ 2266 | Read-only data | 2267 +-------------------+ 2268 | Code | 2269 +-------------------+ BLx_BASE 2270 2271.. note:: 2272 The 2KB alignment for the exception vectors is an architectural 2273 requirement. 2274 2275The read-write data start on a new memory page so that they can be mapped with 2276read-write permissions, whereas the code and read-only data below are configured 2277as read-only. 2278 2279However, the read-only data are not aligned on a page boundary. They are 2280contiguous to the code. Therefore, the end of the code section and the beginning 2281of the read-only data one might share a memory page. This forces both to be 2282mapped with the same memory attributes. As the code needs to be executable, this 2283means that the read-only data stored on the same memory page as the code are 2284executable as well. This could potentially be exploited as part of a security 2285attack. 2286 2287TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2288read-only data on separate memory pages. This in turn allows independent control 2289of the access permissions for the code and read-only data. In this case, 2290platform code gets a finer-grained view of the image layout and can 2291appropriately map the code region as executable and the read-only data as 2292execute-never. 2293 2294This has an impact on memory footprint, as padding bytes need to be introduced 2295between the code and read-only data to ensure the segregation of the two. To 2296limit the memory cost, this flag also changes the memory layout such that the 2297code and exception vectors are now contiguous, like so: 2298 2299:: 2300 2301 | ... | 2302 +-------------------+ 2303 | Read-write data | 2304 +-------------------+ Page boundary 2305 | <Padding> | 2306 +-------------------+ 2307 | Read-only data | 2308 +-------------------+ Page boundary 2309 | <Padding> | 2310 +-------------------+ 2311 | Exception vectors | 2312 +-------------------+ 2 KB boundary 2313 | <Padding> | 2314 +-------------------+ 2315 | Code | 2316 +-------------------+ BLx_BASE 2317 2318With this more condensed memory layout, the separation of read-only data will 2319add zero or one page to the memory footprint of each BL image. Each platform 2320should consider the trade-off between memory footprint and security. 2321 2322This build flag is disabled by default, minimising memory footprint. On Arm 2323platforms, it is enabled. 2324 2325Publish and Subscribe Framework 2326------------------------------- 2327 2328The Publish and Subscribe Framework allows EL3 components to define and publish 2329events, to which other EL3 components can subscribe. 2330 2331The following macros are provided by the framework: 2332 2333- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2334 the event name, which must be a valid C identifier. All calls to 2335 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2336 ``pubsub_events.h``. 2337 2338- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2339 subscribed handlers and calling them in turn. The handlers will be passed the 2340 parameter ``arg``. The expected use-case is to broadcast an event. 2341 2342- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2343 ``NULL`` is passed to subscribed handlers. 2344 2345- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2346 subscribe to ``event``. The handler will be executed whenever the ``event`` 2347 is published. 2348 2349- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2350 subscribed for ``event``. ``subscriber`` must be a local variable of type 2351 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2352 iteration. This macro can be used for those patterns that none of the 2353 ``PUBLISH_EVENT_*()`` macros cover. 2354 2355Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2356result in build error. Subscribing to an undefined event however won't. 2357 2358Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2359signature: 2360 2361.. code:: c 2362 2363 typedef void* (*pubsub_cb_t)(const void *arg); 2364 2365There may be arbitrary number of handlers registered to the same event. The 2366order in which subscribed handlers are notified when that event is published is 2367not defined. Subscribed handlers may be executed in any order; handlers should 2368not assume any relative ordering amongst them. 2369 2370Publishing an event on a PE will result in subscribed handlers executing on that 2371PE only; it won't cause handlers to execute on a different PE. 2372 2373Note that publishing an event on a PE blocks until all the subscribed handlers 2374finish executing on the PE. 2375 2376TF-A generic code publishes and subscribes to some events within. Platform 2377ports are discouraged from subscribing to them. These events may be withdrawn, 2378renamed, or have their semantics altered in the future. Platforms may however 2379register, publish, and subscribe to platform-specific events. 2380 2381Publish and Subscribe Example 2382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2383 2384A publisher that wants to publish event ``foo`` would: 2385 2386- Define the event ``foo`` in the ``pubsub_events.h``. 2387 2388 .. code:: c 2389 2390 REGISTER_PUBSUB_EVENT(foo); 2391 2392- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2393 publish the event at the appropriate path and time of execution. 2394 2395A subscriber that wants to subscribe to event ``foo`` published above would 2396implement: 2397 2398.. code:: c 2399 2400 void *foo_handler(const void *arg) 2401 { 2402 void *result; 2403 2404 /* Do handling ... */ 2405 2406 return result; 2407 } 2408 2409 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2410 2411 2412Reclaiming the BL31 initialization code 2413~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2414 2415A significant amount of the code used for the initialization of BL31 is never 2416needed again after boot time. In order to reduce the runtime memory 2417footprint, the memory used for this code can be reclaimed after initialization 2418has finished and be used for runtime data. 2419 2420The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2421with a ``.text.init.*`` attribute which can be filtered and placed suitably 2422within the BL image for later reclamation by the platform. The platform can 2423specify the filter and the memory region for this init section in BL31 via the 2424plat.ld.S linker script. For example, on the FVP, this section is placed 2425overlapping the secondary CPU stacks so that after the cold boot is done, this 2426memory can be reclaimed for the stacks. The init memory section is initially 2427mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2428completed, the FVP changes the attributes of this section to ``RW``, 2429``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2430are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2431section section can be reclaimed for any data which is accessed after cold 2432boot initialization and it is upto the platform to make the decision. 2433 2434.. _firmware_design_pmf: 2435 2436Performance Measurement Framework 2437--------------------------------- 2438 2439The Performance Measurement Framework (PMF) facilitates collection of 2440timestamps by registered services and provides interfaces to retrieve them 2441from within TF-A. A platform can choose to expose appropriate SMCs to 2442retrieve these collected timestamps. 2443 2444By default, the global physical counter is used for the timestamp 2445value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2446timestamps captured by other CPUs. 2447 2448Timestamp identifier format 2449~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2450 2451A PMF timestamp is uniquely identified across the system via the 2452timestamp ID or ``tid``. The ``tid`` is composed as follows: 2453 2454:: 2455 2456 Bits 0-7: The local timestamp identifier. 2457 Bits 8-9: Reserved. 2458 Bits 10-15: The service identifier. 2459 Bits 16-31: Reserved. 2460 2461#. The service identifier. Each PMF service is identified by a 2462 service name and a service identifier. Both the service name and 2463 identifier are unique within the system as a whole. 2464 2465#. The local timestamp identifier. This identifier is unique within a given 2466 service. 2467 2468Registering a PMF service 2469~~~~~~~~~~~~~~~~~~~~~~~~~ 2470 2471To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2472is used. The arguments required are the service name, the service ID, 2473the total number of local timestamps to be captured and a set of flags. 2474 2475The ``flags`` field can be specified as a bitwise-OR of the following values: 2476 2477:: 2478 2479 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2480 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2481 2482The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2483timestamps in a PMF specific linker section at build time. 2484Additionally, it defines necessary functions to capture and 2485retrieve a particular timestamp for the given service at runtime. 2486 2487The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2488from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2489``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2490accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2491macro but additionally supports retrieving timestamps using SMCs. 2492 2493Capturing a timestamp 2494~~~~~~~~~~~~~~~~~~~~~ 2495 2496PMF timestamps are stored in a per-service timestamp region. On a 2497system with multiple CPUs, each timestamp is captured and stored 2498in a per-CPU cache line aligned memory region. 2499 2500Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2501used to capture a timestamp at the location where it is used. The macro 2502takes the service name, a local timestamp identifier and a flag as arguments. 2503 2504The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2505instructs PMF to do cache maintenance following the capture. Cache 2506maintenance is required if any of the service's timestamps are captured 2507with data cache disabled. 2508 2509To capture a timestamp in assembly code, the caller should use 2510``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2511calculate the address of where the timestamp would be stored. The 2512caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2513and store it at the determined address for later retrieval. 2514 2515Retrieving a timestamp 2516~~~~~~~~~~~~~~~~~~~~~~ 2517 2518From within TF-A, timestamps for individual CPUs can be retrieved using either 2519``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2520These macros accept the CPU's MPIDR value, or its ordinal position 2521respectively. 2522 2523From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2524into ``pmf_smc_handler()``. 2525 2526:: 2527 2528 Interface : pmf_smc_handler() 2529 Argument : unsigned int smc_fid, u_register_t x1, 2530 u_register_t x2, u_register_t x3, 2531 u_register_t x4, void *cookie, 2532 void *handle, u_register_t flags 2533 Return : uintptr_t 2534 2535 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2536 when the caller of the SMC is running in AArch32 mode 2537 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2538 x1: Timestamp identifier. 2539 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2540 This can be the `mpidr` of a different core to the one initiating 2541 the SMC. In that case, service specific cache maintenance may be 2542 required to ensure the updated copy of the timestamp is returned. 2543 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2544 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2545 cache invalidate before reading the timestamp. This ensures 2546 an updated copy is returned. 2547 2548The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2549in this implementation. 2550 2551PMF code structure 2552~~~~~~~~~~~~~~~~~~ 2553 2554#. ``pmf_main.c`` consists of core functions that implement service registration, 2555 initialization, storing, dumping and retrieving timestamps. 2556 2557#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2558 2559#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2560 2561#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2562 assembly code. 2563 2564#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2565 2566Armv8-A Architecture Extensions 2567------------------------------- 2568 2569TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2570section lists the usage of Architecture Extensions, and build flags 2571controlling them. 2572 2573In general, and unless individually mentioned, the build options 2574``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2575target when building TF-A. Subsequent Arm Architecture Extensions are backward 2576compatible with previous versions. 2577 2578The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2579valid numeric value. These build options only control whether or not 2580Architecture Extension-specific code is included in the build. Otherwise, TF-A 2581targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2582and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2583 2584.. seealso:: :ref:`Build Options` 2585 2586For details on the Architecture Extension and available features, please refer 2587to the respective Architecture Extension Supplement. 2588 2589Armv8.1-A 2590~~~~~~~~~ 2591 2592This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2593``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2594 2595- By default, a load-/store-exclusive instruction pair is used to implement 2596 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2597 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2598 Notice this instruction is only available in AArch64 execution state, so 2599 the option is only available to AArch64 builds. 2600 2601Armv8.2-A 2602~~~~~~~~~ 2603 2604- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2605 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2606 Processing Elements in the same Inner Shareable domain use the same 2607 translation table entries for a given stage of translation for a particular 2608 translation regime. 2609 2610Armv8.3-A 2611~~~~~~~~~ 2612 2613- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2614 the Non-secure world so that lower ELs are allowed to use them without 2615 causing a trap to EL3. 2616 2617 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2618 must be set to 1. This will add all pointer authentication system registers 2619 to the context that is saved when doing a world switch. 2620 2621 The TF-A itself has support for pointer authentication at runtime 2622 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2623 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2624 BL2, BL31, and the TSP if it is used. 2625 2626 Note that Pointer Authentication is enabled for Non-secure world irrespective 2627 of the value of these build flags if the CPU supports it. 2628 2629 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2630 enabling PAuth is lower because the compiler will use the optimized 2631 PAuth instructions rather than the backwards-compatible ones. 2632 2633Armv8.5-A 2634~~~~~~~~~ 2635 2636- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2637 option set to 1. This option defaults to 0. 2638 2639- Memory Tagging Extension feature is unconditionally enabled for both worlds 2640 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2641 implemented at all ELs, it is unconditionally enabled for only the normal 2642 world. To enable it for the secure world as well, the build option 2643 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2644 MTE support at all, it is always disabled, no matter what build options 2645 are used. 2646 2647Armv7-A 2648~~~~~~~ 2649 2650This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2651 2652There are several Armv7-A extensions available. Obviously the TrustZone 2653extension is mandatory to support the TF-A bootloader and runtime services. 2654 2655Platform implementing an Armv7-A system can to define from its target 2656Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2657``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2658Cortex-A15 target. 2659 2660Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2661Note that using neon at runtime has constraints on non secure world context. 2662TF-A does not yet provide VFP context management. 2663 2664Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2665the toolchain target architecture directive. 2666 2667Platform may choose to not define straight the toolchain target architecture 2668directive by defining ``MARCH32_DIRECTIVE``. 2669I.e: 2670 2671.. code:: make 2672 2673 MARCH32_DIRECTIVE := -mach=armv7-a 2674 2675Code Structure 2676-------------- 2677 2678TF-A code is logically divided between the three boot loader stages mentioned 2679in the previous sections. The code is also divided into the following 2680categories (present as directories in the source code): 2681 2682- **Platform specific.** Choice of architecture specific code depends upon 2683 the platform. 2684- **Common code.** This is platform and architecture agnostic code. 2685- **Library code.** This code comprises of functionality commonly used by all 2686 other code. The PSCI implementation and other EL3 runtime frameworks reside 2687 as Library components. 2688- **Stage specific.** Code specific to a boot stage. 2689- **Drivers.** 2690- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2691 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2692 2693Each boot loader stage uses code from one or more of the above mentioned 2694categories. Based upon the above, the code layout looks like this: 2695 2696:: 2697 2698 Directory Used by BL1? Used by BL2? Used by BL31? 2699 bl1 Yes No No 2700 bl2 No Yes No 2701 bl31 No No Yes 2702 plat Yes Yes Yes 2703 drivers Yes No Yes 2704 common Yes Yes Yes 2705 lib Yes Yes Yes 2706 services No No Yes 2707 2708The build system provides a non configurable build option IMAGE_BLx for each 2709boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2710defined by the build system. This enables TF-A to compile certain code only 2711for specific boot loader stages 2712 2713All assembler files have the ``.S`` extension. The linker source files for each 2714boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2715linker scripts which have the extension ``.ld``. 2716 2717FDTs provide a description of the hardware platform and are used by the Linux 2718kernel at boot time. These can be found in the ``fdts`` directory. 2719 2720.. rubric:: References 2721 2722- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2723 2724- `Power State Coordination Interface PDD`_ 2725 2726- `SMC Calling Convention`_ 2727 2728- :ref:`Interrupt Management Framework` 2729 2730-------------- 2731 2732*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.* 2733 2734.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2735.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2736.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2737.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2738.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2739.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2740.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2741.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2742 2743.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2744
