1Marvell IOB address decoding bindings
2=====================================
3
4IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
5
6The IOB includes a description of the address decoding configuration.
7
8IOB supports up to n (in CP110 n=24) windows for external memory transaction.
9When a transaction passes through the IOB, its address is compared to each of
10the enabled windows. If there is a hit and it passes the security checks, it is
11advanced to the target port.
12
13Mandatory functions
14-------------------
15
16- marvell_get_iob_memory_map
17     Returns the IOB windows configuration and the number of windows
18
19Mandatory structures
20--------------------
21
22- iob_memory_map
23     Array that includes the configuration of the windows. Every window/entry is
24     a struct which has 3 parameters:
25
26       - Base address of the window
27       - Size of the window
28       - Target-ID of the window
29
30Target ID options
31-----------------
32
33- **0x0** = Internal configuration space
34- **0x1** = MCI0
35- **0x2** = PEX1_X1
36- **0x3** = PEX2_X1
37- **0x4** = PEX0_X4
38- **0x5** = NAND flash
39- **0x6** = RUNIT (NOR/SPI/BootRoom)
40- **0x7** = MCI1
41
42Example
43-------
44
45.. code:: c
46
47	struct addr_map_win iob_memory_map[] = {
48		{0x00000000f7000000,	0x0000000001000000,	PEX1_TID}, /* PEX1_X1 window */
49		{0x00000000f8000000,	0x0000000001000000,	PEX2_TID}, /* PEX2_X1 window */
50		{0x00000000f6000000,	0x0000000001000000,	PEX0_TID}, /* PEX0_X4 window */
51		{0x00000000f9000000,	0x0000000001000000,	NAND_TID}  /* NAND window */
52	};
53