1NXP SoCs - Overview 2===================== 3.. section-numbering:: 4 :suffix: . 5 6The QorIQ family of ARM based SoCs that are supported on TF-A are: 7 81. LX2160A 9 10- SoC Overview: 11 12The LX2160A multicore processor, the highest-performance member of the 13Layerscape family, combines FinFET process technology's low power and 14sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for 15L2/3 packet processing, together with security offload, robust traffic 16management and quality of service. 17 18Details about LX2160A can be found at `lx2160a`_. 19 20- LX2160ARDB Board: 21 22The LX2160A reference design board provides a comprehensive platform 23that enables design and evaluation of the LX2160A or LX2162A processors. It 24comes preloaded with a board support package (BSP) based on a standard Linux 25kernel. 26 27Board details can be fetched from the link: `lx2160ardb`_. 28 292. LS1028A 30 31- SoC Overview: 32 33The Layerscape LS1028A applications processor for industrial and 34automotive includes a time-sensitive networking (TSN) -enabled Ethernet 35switch and Ethernet controllers to support converged IT and OT networks. 36Two powerful 64-bit Arm®v8 cores support real-time processing for 37industrial control and virtual machines for edge computing in the IoT. 38The integrated GPU and LCD controller enable Human-Machine Interface 39(HMI) systems with next-generation interfaces. 40 41Details about LS1028A can be found at `ls1028a`_. 42 43- LS1028ARDB Boards: 44 45The LS1028A reference design board (RDB) is a computing, evaluation, 46and development platform that supports industrial IoT applications, human 47machine interface solutions, and industrial networking. 48 49Details about LS1028A RDB board can be found at `ls1028ardb`_. 50 51Table of supported boot-modes by each platform & platform that needs FIP-DDR: 52----------------------------------------------------------------------------- 53 54+---------------------+---------------------------------------------------------------------+-----------------+ 55| | BOOT_MODE | | 56| PLAT +-------+--------+-------+-------+-------+-------------+--------------+ fip_ddr_needed | 57| | sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | | 58+=====================+=======+========+=======+=======+=======+=============+==============+=================+ 59| lx2160ardb | yes | | | | yes | yes | | yes | 60+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 61| ls1028ardb | yes | | | | yes | yes | | no | 62+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 63 64 65Boot Sequence 66------------- 67:: 68 69+ Secure World | Normal World 70+ EL0 | 71+ | 72+ EL1 BL32(Tee OS) | kernel 73+ ^ | | ^ 74+ | | | | 75+ EL2 | | | BL33(u-boot) 76+ | | | ^ 77+ | v | / 78+ EL3 BootROM --> BL2 --> BL31 ---------------/ 79+ 80 81Boot Sequence with FIP-DDR 82-------------------------- 83:: 84 85+ Secure World | Normal World 86+ EL0 | 87+ | 88+ EL1 fip-ddr BL32(Tee OS) | kernel 89+ ^ | ^ | | ^ 90+ | | | | | | 91+ EL2 | | | | | BL33(u-boot) 92+ | | | | | ^ 93+ | v | v | / 94+ EL3 BootROM --> BL2 -----> BL31 ---------------/ 95+ 96 97DDR Memory Layout 98-------------------------- 99 100NXP Platforms divide DRAM into banks: 101 102- DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h if it is less than 2GB. 103 104- DRAM1 ~ DRAMn Bank: Greater than 2GB belongs to DRAM1 and following banks, and size of DRAMn Bank varies for one platform to others. 105 106The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0. 107 108:: 109 110 high +---------------------------------------------+ 111 | | 112 | Secure EL1 Payload Shared Memory (2 MB) | 113 | | 114 +---------------------------------------------+ 115 | | 116 | Secure Memory (64 MB) | 117 | | 118 +---------------------------------------------+ 119 | | 120 | Non Secure Memory | 121 | | 122 low +---------------------------------------------+ 123 124How to build 125============= 126 127Code Locations 128-------------- 129 130- OP-TEE: 131 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/optee_os>`__ 132 133- U-Boot: 134 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot>`__ 135 136- RCW: 137 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/rcw>`__ 138 139- ddr-phy-binary: Required by platforms that need fip-ddr. 140 `link <https:://github.com/NXP/ddr-phy-binary>`__ 141 142- cst: Required for TBBR. 143 `link <https:://source.codeaurora.org/external/qoriq/qoriq-components/cst>`__ 144 145Build Procedure 146--------------- 147 148- Fetch all the above repositories into local host. 149 150- Prepare AARCH64 toolchain and set the environment variable "CROSS_COMPILE". 151 152 .. code:: shell 153 154 export CROSS_COMPILE=.../bin/aarch64-linux-gnu- 155 156- Build RCW. Refer README from the respective cloned folder for more details. 157 158- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin. 159 For u-boot you can use the <platform>_tfa_defconfig for build. 160 161- Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip. 162 163- Below are the steps to build TF-A images for the supported platforms. 164 165Compilation steps without BL32 166~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 167 168BUILD BL2: 169 170-To compile 171 .. code:: shell 172 173 make PLAT=$PLAT \ 174 BOOT_MODE=<platform_supported_boot_mode> \ 175 RCW=$RCW_BIN \ 176 pbl 177 178BUILD FIP: 179 180 .. code:: shell 181 182 make PLAT=$PLAT \ 183 BOOT_MODE=<platform_supported_boot_mode> \ 184 RCW=$RCW_BIN \ 185 BL33=$UBOOT_SECURE_BIN \ 186 pbl \ 187 fip 188 189Compilation steps with BL32 190~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 191 192BUILD BL2: 193 194-To compile 195 .. code:: shell 196 197 make PLAT=$PLAT \ 198 BOOT_MODE=<platform_supported_boot_mode> \ 199 RCW=$RCW_BIN \ 200 BL32=$TEE_BIN SPD=opteed\ 201 pbl 202 203BUILD FIP: 204 205 .. code:: shell 206 207 make PLAT=$PLAT \ 208 BOOT_MODE=<platform_supported_boot_mode> \ 209 RCW=$RCW_BIN \ 210 BL32=$TEE_BIN SPD=opteed\ 211 BL33=$UBOOT_SECURE_BIN \ 212 pbl \ 213 fip 214 215 216BUILD fip-ddr (Mandatory for certain platforms, refer table above): 217~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 218 219-To compile additional fip-ddr for selected platforms(Refer above table if the platform needs fip-ddr). 220 .. code:: shell 221 222 make PLAT=<platform_name> fip-ddr 223 224 225Deploy ATF Images 226================= 227 228Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd 229should be modified based on the binary size of the image to be copied. 230 231- Deploy ATF images on flexspi-Nor flash Alt Bank from U-Boot prompt. 232 -- Commands to flash images for bl2_xxx.pbl and fip.bin. 233 234 .. code:: shell 235 236 tftp 82000000 $path/bl2_flexspi_nor.pbl; 237 i2c mw 66 50 20;sf probe 0:0; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize; 238 239 tftp 82000000 $path/fip.bin; 240 i2c mw 66 50 20;sf probe 0:0; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize; 241 242 -- Next step is valid for platform where FIP-DDR is needed. 243 244 .. code:: shell 245 246 tftp 82000000 $path/ddr_fip.bin; 247 i2c mw 66 50 20;sf probe 0:0; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize; 248 249 -- Then reset to alternate bank to boot up ATF. 250 251 .. code:: shell 252 253 qixisreset altbank; 254 255- Deploy ATF images on SD/eMMC from U-Boot prompt. 256 -- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512) 257 258 .. code:: shell 259 260 mmc dev <idx>; (idx = 1 for eMMC; idx = 0 for SD) 261 262 tftp 82000000 $path/bl2_<sd>_or_<emmc>.pbl; 263 mmc write 82000000 8 <file_size_in_block_sizeof_512>; 264 265 tftp 82000000 $path/fip.bin; 266 mmc write 82000000 0x800 <file_size_in_block_sizeof_512>; 267 268 -- Next step is valid for platform that needs FIP-DDR. 269 270 .. code:: shell 271 272 tftp 82000000 $path/ddr_fip.bin; 273 mmc write 82000000 0x4000 <file_size_in_block_sizeof_512>; 274 275 -- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source. 276 277 .. code:: shell 278 279 qixisreset <sd or emmc>; 280 281Trusted Board Boot: 282=================== 283 284For TBBR, the binary name changes: 285 286+-------------+--------------------------+---------+-------------------+ 287| Boot Type | BL2 | FIP | FIP-DDR | 288+=============+==========================+=========+===================+ 289| Normal Boot | bl2_<boot_mode>.pbl | fip.bin | ddr_fip.bin | 290+-------------+--------------------------+---------+-------------------+ 291| TBBR Boot | bl2_<boot_mode>_sec.pbl | fip.bin | ddr_fip_sec.bin | 292+-------------+--------------------------+---------+-------------------+ 293 294Refer `nxp-ls-tbbr.rst`_ for detailed user steps. 295 296 297.. _lx2160a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A 298.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A 299.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A 300.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB 301.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst 302