1Advisory TFV-2 (CVE-2017-7564) 2============================== 3 4+----------------+-------------------------------------------------------------+ 5| Title | Enabled secure self-hosted invasive debug interface can | 6| | allow normal world to panic secure world | 7+================+=============================================================+ 8| CVE ID | `CVE-2017-7564`_ | 9+----------------+-------------------------------------------------------------+ 10| Date | 02 Feb 2017 | 11+----------------+-------------------------------------------------------------+ 12| Versions | All versions up to v1.3 | 13| Affected | | 14+----------------+-------------------------------------------------------------+ 15| Configurations | All | 16| Affected | | 17+----------------+-------------------------------------------------------------+ 18| Impact | Denial of Service (secure world panic) | 19+----------------+-------------------------------------------------------------+ 20| Fix Version | 15 Feb 2017 `Pull Request #841`_ | 21+----------------+-------------------------------------------------------------+ 22| Credit | ARM | 23+----------------+-------------------------------------------------------------+ 24 25The ``MDCR_EL3.SDD`` bit controls AArch64 secure self-hosted invasive debug 26enablement. By default, the BL1 and BL31 images of the current version of ARM 27Trusted Firmware (TF) unconditionally assign this bit to ``0`` in the early 28entrypoint code, which enables debug exceptions from the secure world. This can 29be seen in the implementation of the ``el3_arch_init_common`` `AArch64 macro`_ . 30Given that TF does not currently contain support for this feature (for example, 31by saving and restoring the appropriate debug registers), this may allow a 32normal world attacker to induce a panic in the secure world. 33 34The ``MDCR_EL3.SDD`` bit should be assigned to ``1`` to disable debug exceptions 35from the secure world. 36 37Earlier versions of TF (prior to `commit 495f3d3`_) did not assign this bit. 38Since the bit has an architecturally ``UNKNOWN`` reset value, earlier versions 39may or may not have the same problem, depending on the platform. 40 41A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32 42secure self-hosted invasive debug enablement. TF assigns these bits to ``00`` 43meaning that debug exceptions from Secure EL1 are enabled by the authentication 44interface. Therefore this issue only exists for AArch32 Secure EL1 code when 45secure privileged invasive debug is enabled by the authentication interface, at 46which point the device is vulnerable to other, more serious attacks anyway. 47 48However, given that TF contains no support for handling debug exceptions, the 49``MDCR_EL3.SPD32`` bits should be assigned to ``10`` to disable debug exceptions 50from AArch32 Secure EL1. 51 52Finally, this also issue applies to AArch32 platforms that use the TF SP_MIN 53image or integrate the `AArch32 equivalent`_ of the ``el3_arch_init_common`` 54macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to 55``10`` instead of ``00`` 56 57.. _CVE-2017-7564: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-7564 58.. _commit 495f3d3: https://github.com/ARM-software/arm-trusted-firmware/commit/495f3d3 59.. _AArch64 macro: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch64/el3_common_macros.S#L85 60.. _AArch32 equivalent: https://github.com/ARM-software/arm-trusted-firmware/blob/bcc2bf0/include/common/aarch32/el3_common_macros.S#L41 61.. _Pull Request #841: https://github.com/ARM-software/arm-trusted-firmware/pull/841 62