1Advisory TFV-5 (CVE-2017-15031)
2===============================
3
4+----------------+-------------------------------------------------------------+
5| Title          | Not initializing or saving/restoring ``PMCR_EL0`` can leak  |
6|                | secure world timing information                             |
7+================+=============================================================+
8| CVE ID         | `CVE-2017-15031`_                                           |
9+----------------+-------------------------------------------------------------+
10| Date           | 02 Oct 2017, updated on 04 Nov 2019                         |
11+----------------+-------------------------------------------------------------+
12| Versions       | All, up to and including v2.1                               |
13| Affected       |                                                             |
14+----------------+-------------------------------------------------------------+
15| Configurations | All                                                         |
16| Affected       |                                                             |
17+----------------+-------------------------------------------------------------+
18| Impact         | Leakage of sensitive secure world timing information        |
19+----------------+-------------------------------------------------------------+
20| Fix Version    | `Pull Request #1127`_ (merged on 18 October 2017)           |
21|                |                                                             |
22|                | `Commit e290a8fcbc`_ (merged on 23 August 2019)             |
23|                |                                                             |
24|                | `Commit c3e8b0be9b`_ (merged on 27 September 2019)          |
25+----------------+-------------------------------------------------------------+
26| Credit         | Arm, Marek Bykowski                                         |
27+----------------+-------------------------------------------------------------+
28
29The ``PMCR_EL0`` (Performance Monitors Control Register) provides details of the
30Performance Monitors implementation, including the number of counters
31implemented, and configures and controls the counters. If the ``PMCR_EL0.DP``
32bit is set to zero, the cycle counter (when enabled) counts during secure world
33execution, even when prohibited by the debug signals.
34
35Since TF-A does not save and restore ``PMCR_EL0`` when switching between the
36normal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to
37cause leakage of secure world timing information. This register should be added
38to the list of saved/restored registers both when entering EL3 and also
39transitioning to S-EL1.
40
41Furthermore, ``PMCR_EL0.DP`` has an architecturally ``UNKNOWN`` reset value.
42Since Arm TF does not initialize this register, it's possible that on at least
43some implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other
44bits with an architecturally UNKNOWN reset value should be initialized to
45sensible default values in the secure context.
46
47The same issue exists for the equivalent AArch32 register, ``PMCR``, except that
48here ``PMCR_EL0.DP`` architecturally resets to zero.
49
50NOTE: The original pull request referenced above only fixed the issue for S-EL1
51whereas the EL3 was fixed in the later commits.
52
53.. _CVE-2017-15031: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-15031
54.. _Pull Request #1127: https://github.com/ARM-software/arm-trusted-firmware/pull/1127
55.. _Commit e290a8fcbc: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=e290a8fcbc
56.. _Commit c3e8b0be9b: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=c3e8b0be9b
57
58