1 /* 2 * Copyright (c) 2017 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef IPROC_QSPI_H 8 #define IPROC_QSPI_H 9 10 #include <platform_def.h> 11 12 /*SPI configuration enable*/ 13 #define IPROC_QSPI_CLK_SPEED 62500000 14 #define SPI_CPHA (1 << 0) 15 #define SPI_CPOL (1 << 1) 16 #define IPROC_QSPI_MODE0 0 17 #define IPROC_QSPI_MODE3 (SPI_CPOL|SPI_CPHA) 18 19 #define IPROC_QSPI_BUS 0 20 #define IPROC_QSPI_CS 0 21 #define IPROC_QSPI_BASE_REG QSPI_CTRL_BASE_ADDR 22 #define IPROC_QSPI_CRU_CONTROL_REG QSPI_CLK_CTRL 23 24 #define QSPI_AXI_CLK 200000000 25 26 #define QSPI_RETRY_COUNT_US_MAX 200000 27 28 /* Chip attributes */ 29 #define QSPI_REG_BASE IPROC_QSPI_BASE_REG 30 #define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG 31 #define SPBR_DIV_MIN 8U 32 #define SPBR_DIV_MAX 255U 33 #define NUM_CDRAM_BYTES 16U 34 35 /* Register fields */ 36 #define MSPI_SPCR0_MSB_BITS_8 0x00000020 37 38 /* Flash opcode and parameters */ 39 #define CDRAM_PCS0 2 40 #define CDRAM_CONT (1 << 7) 41 #define CDRAM_BITS_EN (1 << 6) 42 #define CDRAM_QUAD_MODE (1 << 8) 43 #define CDRAM_RBIT_INPUT (1 << 10) 44 45 /* MSPI registers */ 46 #define QSPI_MSPI_MODE_REG_BASE (QSPI_REG_BASE + 0x200) 47 #define MSPI_SPCR0_LSB_REG 0x000 48 #define MSPI_SPCR0_MSB_REG 0x004 49 #define MSPI_SPCR1_LSB_REG 0x008 50 #define MSPI_SPCR1_MSB_REG 0x00c 51 #define MSPI_NEWQP_REG 0x010 52 #define MSPI_ENDQP_REG 0x014 53 #define MSPI_SPCR2_REG 0x018 54 #define MSPI_STATUS_REG 0x020 55 #define MSPI_CPTQP_REG 0x024 56 #define MSPI_TXRAM_REG 0x040 57 #define MSPI_RXRAM_REG 0x0c0 58 #define MSPI_CDRAM_REG 0x140 59 #define MSPI_WRITE_LOCK_REG 0x180 60 #define MSPI_DISABLE_FLUSH_GEN_REG 0x184 61 62 #define MSPI_SPCR0_MSB_REG_MSTR_SHIFT 7 63 #define MSPI_SPCR0_MSB_REG_16_BITS_PER_WD_SHIFT (0 << 2) 64 #define MSPI_SPCR0_MSB_REG_MODE_MASK 0x3 65 66 /* BSPI registers */ 67 #define QSPI_BSPI_MODE_REG_BASE QSPI_REG_BASE 68 #define BSPI_MAST_N_BOOT_CTRL_REG 0x008 69 #define BSPI_BUSY_STATUS_REG 0x00c 70 71 #define MSPI_CMD_COMPLETE_MASK 1 72 #define BSPI_BUSY_MASK 1 73 #define MSPI_CTRL_MASK 1 74 75 #define MSPI_SPE (1 << 6) 76 #define MSPI_CONT_AFTER_CMD (1 << 7) 77 78 /* State */ 79 enum bcm_qspi_state { 80 QSPI_STATE_DISABLED, 81 QSPI_STATE_MSPI, 82 QSPI_STATE_BSPI 83 }; 84 85 /* QSPI private data */ 86 struct bcmspi_priv { 87 /* Specified SPI parameters */ 88 uint32_t max_hz; 89 uint32_t spi_mode; 90 91 /* State */ 92 enum bcm_qspi_state state; 93 int mspi_16bit; 94 95 /* Registers */ 96 uintptr_t mspi_hw; 97 uintptr_t bspi_hw; 98 }; 99 100 int iproc_qspi_setup(uint32_t bus, uint32_t cs, 101 uint32_t max_hz, uint32_t mode); 102 int iproc_qspi_claim_bus(void); 103 void iproc_qspi_release_bus(void); 104 int iproc_qspi_xfer(uint32_t bitlen, const void *dout, 105 void *din, unsigned long flags); 106 107 #endif /* _IPROC_QSPI_H_ */ 108