1 /*
2 * Copyright (C) 2016 - 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* IOW unit device driver for Marvell CP110 and CP115 SoCs */
9
10 #include <inttypes.h>
11 #include <stdint.h>
12
13 #include <arch_helpers.h>
14 #include <common/debug.h>
15 #include <drivers/marvell/iob.h>
16 #include <lib/mmio.h>
17
18 #include <armada_common.h>
19 #include <mvebu.h>
20 #include <mvebu_def.h>
21
22 #if LOG_LEVEL >= LOG_LEVEL_INFO
23 #define DEBUG_ADDR_MAP
24 #endif
25
26 #define MVEBU_IOB_OFFSET (0x190000)
27 #define MVEBU_IOB_MAX_WINS 16
28
29 /* common defines */
30 #define WIN_ENABLE_BIT (0x1)
31 /* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
32 #define ADDRESS_SHIFT (20 - 4)
33 #define ADDRESS_MASK (0xFFFFFFF0)
34 #define IOB_WIN_ALIGNMENT (0x100000)
35
36 /* IOB registers */
37 #define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win))
38 #define IOB_TARGET_ID_OFFSET (8)
39 #define IOB_TARGET_ID_MASK (0xF)
40
41 #define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win))
42 #define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1)
43 #define IOB_WIN_ENA_CTRL_READ_SECURE (0x2)
44 #define IOB_WIN_ENA_WRITE_SECURE (0x4)
45 #define IOB_WIN_ENA_READ_SECURE (0x8)
46
47 #define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
48 #define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
49
50 #define IOB_WIN_DIOB_CR_OFFSET(win) (iob_base + 0x10 + (0x20 * win))
51 #define IOB_WIN_XOR0_DIOB_EN BIT(0)
52 #define IOB_WIN_XOR1_DIOB_EN BIT(1)
53
54 uintptr_t iob_base;
55
iob_win_check(struct addr_map_win * win,uint32_t win_num)56 static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
57 {
58 /* check if address is aligned to the size */
59 if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
60 win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
61 ERROR("Window %d: base address unaligned to 0x%x\n",
62 win_num, IOB_WIN_ALIGNMENT);
63 printf("Align up the base address to 0x%" PRIx64 "\n",
64 win->base_addr);
65 }
66
67 /* size parameter validity check */
68 if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
69 win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
70 ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
71 IOB_WIN_ALIGNMENT);
72 printf("Aligning size to 0x%" PRIx64 "\n", win->win_size);
73 }
74 }
75
iob_enable_win(struct addr_map_win * win,uint32_t win_id)76 static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
77 {
78 uint32_t iob_win_reg;
79 uint32_t alr, ahr;
80 uint64_t end_addr;
81 uint32_t reg_en;
82
83 /* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */
84 reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN;
85 iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0));
86 iob_win_reg &= ~reg_en;
87 mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg);
88
89 iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1));
90 iob_win_reg |= reg_en;
91 mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg);
92
93 end_addr = (win->base_addr + win->win_size - 1);
94 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
95 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
96
97 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
98 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
99
100 iob_win_reg = WIN_ENABLE_BIT;
101 iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
102 << IOB_TARGET_ID_OFFSET;
103 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
104
105 }
106
107 #ifdef DEBUG_ADDR_MAP
dump_iob(void)108 static void dump_iob(void)
109 {
110 uint32_t win_id, win_cr, alr, ahr;
111 uint8_t target_id;
112 uint64_t start, end;
113 char *iob_target_name[IOB_MAX_TID] = {
114 "CFG ", "MCI0 ", "PEX1 ", "PEX2 ",
115 "PEX0 ", "NAND ", "RUNIT", "MCI1 " };
116
117 /* Dump all IOB windows */
118 printf("bank id target start end\n");
119 printf("----------------------------------------------------\n");
120 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
121 win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
122 if (win_cr & WIN_ENABLE_BIT) {
123 target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
124 IOB_TARGET_ID_MASK;
125 alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
126 start = ((uint64_t)alr << ADDRESS_SHIFT);
127 if (win_id != 0) {
128 ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
129 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
130 } else {
131 /* Window #0 size is hardcoded to 16MB, as it's
132 * reserved for CP configuration space.
133 */
134 end = start + (16 << 20);
135 }
136 printf("iob %02d %s 0x%016" PRIx64 " 0x%016" PRIx64 "\n",
137 win_id, iob_target_name[target_id],
138 start, end);
139 }
140 }
141 }
142 #endif
143
iob_cfg_space_update(int ap_idx,int cp_idx,uintptr_t base,uintptr_t new_base)144 void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
145 uintptr_t new_base)
146 {
147 debug_enter();
148
149 iob_base = base + MVEBU_IOB_OFFSET;
150
151 NOTICE("Change the base address of AP%d-CP%d to %lx\n",
152 ap_idx, cp_idx, new_base);
153 mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
154
155 iob_base = new_base + MVEBU_IOB_OFFSET;
156
157 /* Make sure the address was configured by the CPU before
158 * any possible access to the CP.
159 */
160 dsb();
161
162 debug_exit();
163 }
164
init_iob(uintptr_t base)165 int init_iob(uintptr_t base)
166 {
167 struct addr_map_win *win;
168 uint32_t win_id, win_reg;
169 uint32_t win_count;
170
171 INFO("Initializing IOB Address decoding\n");
172
173 /* Get the base address of the address decoding MBUS */
174 iob_base = base + MVEBU_IOB_OFFSET;
175
176 /* Get the array of the windows and fill the map data */
177 marvell_get_iob_memory_map(&win, &win_count, base);
178 if (win_count <= 0) {
179 INFO("no windows configurations found\n");
180 return 0;
181 } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
182 ERROR("IOB mem map array > than max available windows (%d)\n",
183 MVEBU_IOB_MAX_WINS);
184 win_count = MVEBU_IOB_MAX_WINS;
185 }
186
187 /* disable all IOB windows, start from win_id = 1
188 * because can't disable internal register window
189 */
190 for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
191 win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
192 win_reg &= ~WIN_ENABLE_BIT;
193 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
194
195 win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
196 win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
197 win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
198 win_reg &= ~IOB_WIN_ENA_READ_SECURE;
199 mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
200 }
201
202 for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
203 iob_win_check(win, win_id);
204 iob_enable_win(win, win_id);
205 }
206
207 #ifdef DEBUG_ADDR_MAP
208 dump_iob();
209 #endif
210
211 INFO("Done IOB Address decoding Initializing\n");
212
213 return 0;
214 }
215