1 /*
2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9
10 #include "cpg_registers.h"
11 #include "iic_dvfs.h"
12 #include "rcar_def.h"
13 #include "rcar_private.h"
14
15 #define DVFS_RETRY_MAX (2U)
16
17 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U)
18 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U)
19 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU)
20 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU)
21 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15U)
22
23 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U)
24 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U)
25 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U)
26 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U)
27 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07U)
28
29 #define CPG_BIT_SMSTPCR9_DVFS (0x04000000U)
30
31 #define IIC_DVFS_REG_BASE (0xE60B0000U)
32 #define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U)
33 #define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U)
34 #define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U)
35 #define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU)
36 #define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U)
37 #define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U)
38
39 #define IIC_DVFS_BIT_ICSR_BUSY (0x10U)
40 #define IIC_DVFS_BIT_ICSR_AL (0x08U)
41 #define IIC_DVFS_BIT_ICSR_TACK (0x04U)
42 #define IIC_DVFS_BIT_ICSR_WAIT (0x02U)
43 #define IIC_DVFS_BIT_ICSR_DTE (0x01U)
44
45 #define IIC_DVFS_BIT_ICCR_ENABLE (0x80U)
46 #define IIC_DVFS_SET_ICCR_START (0x94U)
47 #define IIC_DVFS_SET_ICCR_STOP (0x90U)
48 #define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U)
49 #define IIC_DVFS_SET_ICCR_CHANGE (0x81U)
50 #define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U)
51
52 #define IIC_DVFS_BIT_ICIC_TACKE (0x04U)
53 #define IIC_DVFS_BIT_ICIC_WAITE (0x02U)
54 #define IIC_DVFS_BIT_ICIC_DTEE (0x01U)
55
56 #define DVFS_READ_MODE (0x01U)
57 #define DVFS_WRITE_MODE (0x00U)
58
59 #define IIC_DVFS_SET_DUMMY (0x52U)
60 #define IIC_DVFS_SET_BUSY_LOOP (500000000U)
61
62 enum dvfs_state_t {
63 DVFS_START = 0,
64 DVFS_STOP,
65 DVFS_RETRANSMIT,
66 DVFS_READ,
67 DVFS_STOP_READ,
68 DVFS_SET_SLAVE_READ,
69 DVFS_SET_SLAVE,
70 DVFS_WRITE_ADDR,
71 DVFS_WRITE_DATA,
72 DVFS_CHANGE_SEND_TO_RECEIVE,
73 DVFS_DONE,
74 };
75
76 #define DVFS_PROCESS (1)
77 #define DVFS_COMPLETE (0)
78 #define DVFS_ERROR (-1)
79
80 #if IMAGE_BL31
81 #define IIC_DVFS_FUNC(__name, ...) \
82 static int32_t __attribute__ ((section(".system_ram"))) \
83 dvfs_ ##__name(__VA_ARGS__)
84
85 #define RCAR_DVFS_API(__name, ...) \
86 int32_t __attribute__ ((section(".system_ram"))) \
87 rcar_iic_dvfs_ ##__name(__VA_ARGS__)
88
89 #else
90 #define IIC_DVFS_FUNC(__name, ...) \
91 static int32_t dvfs_ ##__name(__VA_ARGS__)
92
93 #define RCAR_DVFS_API(__name, ...) \
94 int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
95 #endif
96
IIC_DVFS_FUNC(check_error,enum dvfs_state_t * state,uint32_t * err,uint8_t mode)97 IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode)
98 {
99 uint8_t icsr_al = 0U, icsr_tack = 0U;
100 uint8_t reg, stop;
101 uint32_t i = 0U;
102
103 stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
104 IIC_DVFS_SET_ICCR_STOP;
105
106 reg = mmio_read_8(IIC_DVFS_REG_ICSR);
107 icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
108 icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
109
110 if (icsr_al == 0U && icsr_tack == 0U) {
111 return DVFS_PROCESS;
112 }
113
114 if (icsr_al) {
115 reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
116 mmio_write_8(IIC_DVFS_REG_ICSR, reg);
117
118 if (*state == DVFS_SET_SLAVE) {
119 mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
120 }
121
122 do {
123 reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
124 IIC_DVFS_BIT_ICSR_WAIT;
125 } while (reg == 0U);
126
127 mmio_write_8(IIC_DVFS_REG_ICCR, stop);
128
129 reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
130 mmio_write_8(IIC_DVFS_REG_ICSR, reg);
131
132 i = 0U;
133 do {
134 reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
135 IIC_DVFS_BIT_ICSR_BUSY;
136 if (reg == 0U) {
137 break;
138 }
139
140 if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
141 panic();
142 }
143
144 } while (true);
145
146 mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
147
148 (*err)++;
149 if (*err > DVFS_RETRY_MAX) {
150 return DVFS_ERROR;
151 }
152
153 *state = DVFS_START;
154
155 return DVFS_PROCESS;
156
157 }
158
159 /* icsr_tack */
160 mmio_write_8(IIC_DVFS_REG_ICCR, stop);
161
162 reg = mmio_read_8(IIC_DVFS_REG_ICIC);
163 reg &= ~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE);
164 mmio_write_8(IIC_DVFS_REG_ICIC, reg);
165
166 reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
167 mmio_write_8(IIC_DVFS_REG_ICSR, reg);
168
169 i = 0U;
170 while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
171 if (i++ > IIC_DVFS_SET_BUSY_LOOP) {
172 panic();
173 }
174 }
175
176 mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
177 (*err)++;
178
179 if (*err > DVFS_RETRY_MAX) {
180 return DVFS_ERROR;
181 }
182
183 *state = DVFS_START;
184
185 return DVFS_PROCESS;
186 }
187
IIC_DVFS_FUNC(start,enum dvfs_state_t * state)188 IIC_DVFS_FUNC(start, enum dvfs_state_t *state)
189 {
190 uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
191 uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
192 int32_t result = DVFS_PROCESS;
193 uint32_t reg, lsi_product;
194 uint8_t mode;
195
196 mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
197 mmio_write_8(IIC_DVFS_REG_ICCR, mode);
198
199 lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
200 if (lsi_product == PRR_PRODUCT_E3) {
201 goto start;
202 }
203
204 reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
205 switch (reg) {
206 case MD14_MD13_TYPE_0:
207 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_0;
208 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_0;
209 break;
210 case MD14_MD13_TYPE_1:
211 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_1;
212 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_1;
213 break;
214 case MD14_MD13_TYPE_2:
215 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_2;
216 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_2;
217 break;
218 default:
219 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_3;
220 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_3;
221 break;
222 }
223 start:
224 mmio_write_8(IIC_DVFS_REG_ICCL, iccl);
225 mmio_write_8(IIC_DVFS_REG_ICCH, icch);
226
227 mode = mmio_read_8(IIC_DVFS_REG_ICIC)
228 | IIC_DVFS_BIT_ICIC_TACKE
229 | IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE;
230
231 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
232 mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START);
233
234 *state = DVFS_SET_SLAVE;
235
236 return result;
237 }
238
IIC_DVFS_FUNC(set_slave,enum dvfs_state_t * state,uint32_t * err,uint8_t slave)239 IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave)
240 {
241 uint8_t mode;
242 int32_t result;
243 uint8_t address;
244
245 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
246 if (result == DVFS_ERROR) {
247 return result;
248 }
249
250 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
251 if (mode != IIC_DVFS_BIT_ICSR_DTE) {
252 return result;
253 }
254
255 mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
256 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
257
258 address = slave << 1;
259 mmio_write_8(IIC_DVFS_REG_ICDR, address);
260
261 *state = DVFS_WRITE_ADDR;
262
263 return result;
264 }
265
IIC_DVFS_FUNC(write_addr,enum dvfs_state_t * state,uint32_t * err,uint8_t reg_addr)266 IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr)
267 {
268 uint8_t mode;
269 int32_t result;
270
271 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
272 if (result == DVFS_ERROR) {
273 return result;
274 }
275
276 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
277 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
278 return result;
279 }
280
281 mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
282
283 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
284 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
285
286 *state = DVFS_WRITE_DATA;
287
288 return result;
289 }
290
IIC_DVFS_FUNC(write_data,enum dvfs_state_t * state,uint32_t * err,uint8_t reg_data)291 IIC_DVFS_FUNC(write_data, enum dvfs_state_t *state, uint32_t *err,
292 uint8_t reg_data)
293 {
294 int32_t result;
295 uint8_t mode;
296
297 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
298 if (result == DVFS_ERROR) {
299 return result;
300 }
301
302 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
303 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
304 return result;
305 }
306
307 mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
308
309 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
310 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
311
312 *state = DVFS_STOP;
313
314 return result;
315 }
316
IIC_DVFS_FUNC(stop,enum dvfs_state_t * state,uint32_t * err)317 IIC_DVFS_FUNC(stop, enum dvfs_state_t *state, uint32_t *err)
318 {
319 int32_t result;
320 uint8_t mode;
321
322 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
323 if (result == DVFS_ERROR) {
324 return result;
325 }
326
327 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
328 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
329 return result;
330 }
331
332 mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
333
334 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
335 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
336
337 *state = DVFS_DONE;
338
339 return result;
340 }
341
IIC_DVFS_FUNC(done,void)342 IIC_DVFS_FUNC(done, void)
343 {
344 uint32_t i;
345
346 for (i = 0U; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
347 if ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0U) {
348 continue;
349 }
350 goto done;
351 }
352
353 panic();
354 done:
355 mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
356
357 return DVFS_COMPLETE;
358 }
359
IIC_DVFS_FUNC(write_reg_addr_read,enum dvfs_state_t * state,uint32_t * err,uint8_t reg_addr)360 IIC_DVFS_FUNC(write_reg_addr_read, enum dvfs_state_t *state, uint32_t *err,
361 uint8_t reg_addr)
362 {
363 int32_t result;
364 uint8_t mode;
365
366 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
367 if (result == DVFS_ERROR) {
368 return result;
369 }
370
371 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
372 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
373 return result;
374 }
375
376 mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
377
378 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
379 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
380
381 *state = DVFS_RETRANSMIT;
382
383 return result;
384 }
385
IIC_DVFS_FUNC(retransmit,enum dvfs_state_t * state,uint32_t * err)386 IIC_DVFS_FUNC(retransmit, enum dvfs_state_t *state, uint32_t *err)
387 {
388 int32_t result;
389 uint8_t mode;
390
391 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
392 if (result == DVFS_ERROR) {
393 return result;
394 }
395
396 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
397 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
398 return result;
399 }
400
401 mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
402
403 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
404 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
405
406 mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
407 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
408
409 *state = DVFS_SET_SLAVE_READ;
410
411 return result;
412 }
413
IIC_DVFS_FUNC(set_slave_read,enum dvfs_state_t * state,uint32_t * err,uint8_t slave)414 IIC_DVFS_FUNC(set_slave_read, enum dvfs_state_t *state, uint32_t *err,
415 uint8_t slave)
416 {
417 uint8_t address;
418 int32_t result;
419 uint8_t mode;
420
421 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
422 if (result == DVFS_ERROR) {
423 return result;
424 }
425
426 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
427 if (mode != IIC_DVFS_BIT_ICSR_DTE) {
428 return result;
429 }
430
431 mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
432 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
433
434 address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
435 mmio_write_8(IIC_DVFS_REG_ICDR, address);
436
437 *state = DVFS_CHANGE_SEND_TO_RECEIVE;
438
439 return result;
440 }
441
IIC_DVFS_FUNC(change_send_to_receive,enum dvfs_state_t * state,uint32_t * err)442 IIC_DVFS_FUNC(change_send_to_receive, enum dvfs_state_t *state, uint32_t *err)
443 {
444 int32_t result;
445 uint8_t mode;
446
447 result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
448 if (result == DVFS_ERROR) {
449 return result;
450 }
451
452 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
453 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
454 return result;
455 }
456
457 mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
458
459 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
460 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
461
462 *state = DVFS_STOP_READ;
463
464 return result;
465 }
466
IIC_DVFS_FUNC(stop_read,enum dvfs_state_t * state,uint32_t * err)467 IIC_DVFS_FUNC(stop_read, enum dvfs_state_t *state, uint32_t *err)
468 {
469 int32_t result;
470 uint8_t mode;
471
472 result = dvfs_check_error(state, err, DVFS_READ_MODE);
473 if (result == DVFS_ERROR) {
474 return result;
475 }
476
477 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
478 if (mode != IIC_DVFS_BIT_ICSR_WAIT) {
479 return result;
480 }
481
482 mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
483
484 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
485 mmio_write_8(IIC_DVFS_REG_ICSR, mode);
486
487 mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
488 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
489
490 *state = DVFS_READ;
491
492 return result;
493 }
494
IIC_DVFS_FUNC(read,enum dvfs_state_t * state,uint8_t * reg_data)495 IIC_DVFS_FUNC(read, enum dvfs_state_t *state, uint8_t *reg_data)
496 {
497 uint8_t mode;
498
499 mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
500 if (mode != IIC_DVFS_BIT_ICSR_DTE) {
501 return DVFS_PROCESS;
502 }
503
504 mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
505 mmio_write_8(IIC_DVFS_REG_ICIC, mode);
506
507 *reg_data = mmio_read_8(IIC_DVFS_REG_ICDR);
508 *state = DVFS_DONE;
509
510 return DVFS_PROCESS;
511 }
512
RCAR_DVFS_API(send,uint8_t slave,uint8_t reg_addr,uint8_t reg_data)513 RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
514 {
515 enum dvfs_state_t state = DVFS_START;
516 int32_t result = DVFS_PROCESS;
517 uint32_t err = 0U;
518
519 mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
520 mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
521 again:
522 switch (state) {
523 case DVFS_START:
524 result = dvfs_start(&state);
525 break;
526 case DVFS_SET_SLAVE:
527 result = dvfs_set_slave(&state, &err, slave);
528 break;
529 case DVFS_WRITE_ADDR:
530 result = dvfs_write_addr(&state, &err, reg_addr);
531 break;
532 case DVFS_WRITE_DATA:
533 result = dvfs_write_data(&state, &err, reg_data);
534 break;
535 case DVFS_STOP:
536 result = dvfs_stop(&state, &err);
537 break;
538 case DVFS_DONE:
539 result = dvfs_done();
540 break;
541 default:
542 panic();
543 break;
544 }
545
546 if (result == DVFS_PROCESS) {
547 goto again;
548 }
549
550 return result;
551 }
552
RCAR_DVFS_API(receive,uint8_t slave,uint8_t reg,uint8_t * data)553 RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
554 {
555 enum dvfs_state_t state = DVFS_START;
556 int32_t result = DVFS_PROCESS;
557 uint32_t err = 0U;
558
559 mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
560 mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
561 again:
562 switch (state) {
563 case DVFS_START:
564 result = dvfs_start(&state);
565 break;
566 case DVFS_SET_SLAVE:
567 result = dvfs_set_slave(&state, &err, slave);
568 break;
569 case DVFS_WRITE_ADDR:
570 result = dvfs_write_reg_addr_read(&state, &err, reg);
571 break;
572 case DVFS_RETRANSMIT:
573 result = dvfs_retransmit(&state, &err);
574 break;
575 case DVFS_SET_SLAVE_READ:
576 result = dvfs_set_slave_read(&state, &err, slave);
577 break;
578 case DVFS_CHANGE_SEND_TO_RECEIVE:
579 result = dvfs_change_send_to_receive(&state, &err);
580 break;
581 case DVFS_STOP_READ:
582 result = dvfs_stop_read(&state, &err);
583 break;
584 case DVFS_READ:
585 result = dvfs_read(&state, data);
586 break;
587 case DVFS_DONE:
588 result = dvfs_done();
589 break;
590 default:
591 panic();
592 break;
593 }
594
595 if (result == DVFS_PROCESS) {
596 goto again;
597 }
598
599 return result;
600 }
601