1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10
11 #include "../qos_common.h"
12 #include "../qos_reg.h"
13 #include "qos_init_d3.h"
14
15 #define RCAR_QOS_VERSION "rev.0.05"
16
17 #include "qos_init_d3_mstat.h"
18
19 struct rcar_gen3_dbsc_qos_settings d3_qos[] = {
20 /* BUFCAM settings */
21 { DBSC_DBCAM0CNF1, 0x00043218 },
22 { DBSC_DBCAM0CNF2, 0x000000F4 },
23 { DBSC_DBSCHCNT0, 0x000F0037 },
24 { DBSC_DBSCHSZ0, 0x00000001 },
25 { DBSC_DBSCHRW0, 0x22421111 },
26
27 /* DDR3 */
28 { DBSC_SCFCTST2, 0x012F1123 },
29
30 /* QoS Settings */
31 { DBSC_DBSCHQOS00, 0x00000F00 },
32 { DBSC_DBSCHQOS01, 0x00000B00 },
33 { DBSC_DBSCHQOS02, 0x00000000 },
34 { DBSC_DBSCHQOS03, 0x00000000 },
35 { DBSC_DBSCHQOS40, 0x00000300 },
36 { DBSC_DBSCHQOS41, 0x000002F0 },
37 { DBSC_DBSCHQOS42, 0x00000200 },
38 { DBSC_DBSCHQOS43, 0x00000100 },
39 { DBSC_DBSCHQOS90, 0x00000300 },
40 { DBSC_DBSCHQOS91, 0x000002F0 },
41 { DBSC_DBSCHQOS92, 0x00000200 },
42 { DBSC_DBSCHQOS93, 0x00000100 },
43 { DBSC_DBSCHQOS130, 0x00000100 },
44 { DBSC_DBSCHQOS131, 0x000000F0 },
45 { DBSC_DBSCHQOS132, 0x000000A0 },
46 { DBSC_DBSCHQOS133, 0x00000040 },
47 { DBSC_DBSCHQOS140, 0x000000C0 },
48 { DBSC_DBSCHQOS141, 0x000000B0 },
49 { DBSC_DBSCHQOS142, 0x00000080 },
50 { DBSC_DBSCHQOS143, 0x00000040 },
51 { DBSC_DBSCHQOS150, 0x00000040 },
52 { DBSC_DBSCHQOS151, 0x00000030 },
53 { DBSC_DBSCHQOS152, 0x00000020 },
54 { DBSC_DBSCHQOS153, 0x00000010 },
55 };
56
qos_init_d3(void)57 void qos_init_d3(void)
58 {
59 rcar_qos_dbsc_setting(d3_qos, ARRAY_SIZE(d3_qos), true);
60
61 /* DRAM Split Address mapping */
62 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
63 ERROR("DRAM Split 4ch not supported.(D3)");
64 panic();
65 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
66 ERROR("DRAM Split 2ch not supported.(D3)");
67 panic();
68 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO
69 ERROR("DRAM Split Auto not supported.(D3)");
70 panic();
71 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_LINEAR
72 /* NOTICE("BL2: DRAM Split is OFF\n"); */
73 /* Split setting(DDR 1ch) */
74 io_write_32(AXI_ADSPLCR0, 0x00000000U);
75 io_write_32(AXI_ADSPLCR3, 0x00000000U);
76 #else
77 ERROR("DRAM split is an invalid value.(D3)");
78 panic();
79 #endif
80
81 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
82 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
83 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
84 #endif
85
86 /* Resource Alloc setting */
87 io_write_32(QOSCTRL_RAS, 0x00000020U);
88 io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
89 io_write_32(QOSCTRL_RAEN, 0x00000001U);
90 io_write_32(QOSCTRL_REGGD, 0x00000000U);
91 io_write_64(QOSCTRL_DANN, 0x0404020002020201U);
92 io_write_32(QOSCTRL_DANT, 0x00100804U);
93 io_write_32(QOSCTRL_EC, 0x00000000U);
94 io_write_64(QOSCTRL_EMS, 0x0000000000000000U);
95 io_write_32(QOSCTRL_FSS, 0x0000000AU);
96 io_write_32(QOSCTRL_INSFC, 0xC7840001U);
97 io_write_32(QOSCTRL_BERR, 0x00000000U);
98 io_write_32(QOSCTRL_EARLYR, 0x00000000U);
99 io_write_32(QOSCTRL_RACNT0, 0x00010003U);
100 io_write_32(QOSCTRL_STATGEN0, 0x00000000U);
101
102 /* GPU setting */
103 io_write_32(0xFD812030U, 0x00000000U);
104
105 /* QOSBW setting */
106 io_write_32(QOSCTRL_SL_INIT, 0x030500ACU);
107 io_write_32(QOSCTRL_REF_ARS, 0x00780000U);
108
109 /* QOSBW SRAM setting */
110 uint32_t i;
111
112 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
113 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
114 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
115 }
116 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
117 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
118 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
119 }
120
121 /* 3DG bus Leaf setting */
122 io_write_32(GPU_ACT_GRD, 0x00001234U);
123 io_write_32(GPU_ACT0, 0x00000000U);
124 io_write_32(GPU_ACT1, 0x00000000U);
125 io_write_32(GPU_ACT2, 0x00000000U);
126 io_write_32(GPU_ACT3, 0x00000000U);
127
128 /* RT bus Leaf setting */
129 io_write_32(CPU_ACT0, 0x00000003U);
130 io_write_32(CPU_ACT1, 0x00000003U);
131 io_write_32(RT_ACT0, 0x00000000U);
132 io_write_32(RT_ACT1, 0x00000000U);
133
134 /* Resource Alloc start */
135 io_write_32(QOSCTRL_RAEN, 0x00000001U);
136
137 /* QOSBW start */
138 io_write_32(QOSCTRL_STATQC, 0x00000001U);
139 #else
140 NOTICE("BL2: QoS is None\n");
141
142 /* Resource Alloc setting */
143 io_write_32(QOSCTRL_EC, 0x00000000U);
144 /* Resource Alloc start */
145 io_write_32(QOSCTRL_RAEN, 0x00000001U);
146 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
147 }
148