1 /*
2 * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10
11 #include "../qos_common.h"
12 #include "../qos_reg.h"
13 #include "qos_init_h3_v30.h"
14
15 #define RCAR_QOS_VERSION "rev.0.11"
16
17 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */
18
19 #define QOSWT_WTEN_ENABLE 0x1U
20
21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 (SL_INIT_SSLOTCLK_H3_30 - 0x5U)
22
23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
25 #define QOSWT_WTREF_SLOT0_EN \
26 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
27 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
28 #define QOSWT_WTREF_SLOT1_EN \
29 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
30 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
31
32 #define QOSWT_WTSET0_REQ_SSLOT0 5U
33 #define WT_BASE_SUB_SLOT_NUM0 12U
34 #define QOSWT_WTSET0_PERIOD0_H3_30 \
35 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3_30) - 1U)
36 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
37 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
38
39 #define QOSWT_WTSET1_PERIOD1_H3_30 (QOSWT_WTSET0_PERIOD0_H3_30)
40 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
41 #define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
42
43 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
44
45 #if RCAR_REF_INT == RCAR_REF_DEFAULT
46 #include "qos_init_h3_v30_mstat195.h"
47 #else
48 #include "qos_init_h3_v30_mstat390.h"
49 #endif
50
51 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
52
53 #if RCAR_REF_INT == RCAR_REF_DEFAULT
54 #include "qos_init_h3_v30_qoswt195.h"
55 #else
56 #include "qos_init_h3_v30_qoswt390.h"
57 #endif
58
59 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
60
61 #endif
62
63 struct rcar_gen3_dbsc_qos_settings h3_v30_qos[] = {
64 /* BUFCAM settings */
65 { DBSC_DBCAM0CNF1, 0x00043218U },
66 { DBSC_DBCAM0CNF2, 0x000000F4U },
67 { DBSC_DBCAM0CNF3, 0x00000000U },
68 { DBSC_DBSCHCNT0, 0x000F0037U },
69 { DBSC_DBSCHSZ0, 0x00000001U },
70 { DBSC_DBSCHRW0, 0x22421111U },
71
72 /* DDR3 */
73 { DBSC_SCFCTST2, 0x012F1123U },
74
75 /* QoS Settings */
76 { DBSC_DBSCHQOS00, 0x00000F00U },
77 { DBSC_DBSCHQOS01, 0x00000B00U },
78 { DBSC_DBSCHQOS02, 0x00000000U },
79 { DBSC_DBSCHQOS03, 0x00000000U },
80 { DBSC_DBSCHQOS40, 0x00000300U },
81 { DBSC_DBSCHQOS41, 0x000002F0U },
82 { DBSC_DBSCHQOS42, 0x00000200U },
83 { DBSC_DBSCHQOS43, 0x00000100U },
84 { DBSC_DBSCHQOS90, 0x00000100U },
85 { DBSC_DBSCHQOS91, 0x000000F0U },
86 { DBSC_DBSCHQOS92, 0x000000A0U },
87 { DBSC_DBSCHQOS93, 0x00000040U },
88 { DBSC_DBSCHQOS120, 0x00000040U },
89 { DBSC_DBSCHQOS121, 0x00000030U },
90 { DBSC_DBSCHQOS122, 0x00000020U },
91 { DBSC_DBSCHQOS123, 0x00000010U },
92 { DBSC_DBSCHQOS130, 0x00000100U },
93 { DBSC_DBSCHQOS131, 0x000000F0U },
94 { DBSC_DBSCHQOS132, 0x000000A0U },
95 { DBSC_DBSCHQOS133, 0x00000040U },
96 { DBSC_DBSCHQOS140, 0x000000C0U },
97 { DBSC_DBSCHQOS141, 0x000000B0U },
98 { DBSC_DBSCHQOS142, 0x00000080U },
99 { DBSC_DBSCHQOS143, 0x00000040U },
100 { DBSC_DBSCHQOS150, 0x00000040U },
101 { DBSC_DBSCHQOS151, 0x00000030U },
102 { DBSC_DBSCHQOS152, 0x00000020U },
103 { DBSC_DBSCHQOS153, 0x00000010U },
104 };
105
qos_init_h3_v30(void)106 void qos_init_h3_v30(void)
107 {
108 unsigned int split_area;
109
110 rcar_qos_dbsc_setting(h3_v30_qos, ARRAY_SIZE(h3_v30_qos), true);
111
112 #if RCAR_DRAM_LPDDR4_MEMCONF == 0 /* 1GB */
113 split_area = 0x1BU;
114 #else /* default 2GB */
115 split_area = 0x1CU;
116 #endif
117
118 /* DRAM Split Address mapping */
119 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
120 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
121 NOTICE("BL2: DRAM Split is 4ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
122
123 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
124 | ADSPLCR0_SPLITSEL(0xFFU)
125 | ADSPLCR0_AREA(split_area)
126 | ADSPLCR0_SWP);
127 io_write_32(AXI_ADSPLCR1, 0x00000000U);
128 io_write_32(AXI_ADSPLCR2, 0x00001054U);
129 io_write_32(AXI_ADSPLCR3, 0x00000000U);
130 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
131 NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
132
133 io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
134 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
135 | ADSPLCR0_SPLITSEL(0xFFU)
136 | ADSPLCR0_AREA(split_area)
137 | ADSPLCR0_SWP);
138 io_write_32(AXI_ADSPLCR2, 0x00001004U);
139 io_write_32(AXI_ADSPLCR3, 0x00000000U);
140 #else
141 io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
142 NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
143 #endif
144
145 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
146 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
147 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
148 #endif
149
150 #if RCAR_REF_INT == RCAR_REF_DEFAULT
151 NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
152 #else
153 NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
154 #endif
155
156 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
157 NOTICE("BL2: Periodic Write DQ Training\n");
158 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
159
160 io_write_32(QOSCTRL_RAS, 0x00000044U);
161 io_write_64(QOSCTRL_DANN, 0x0404010002020201UL);
162 io_write_32(QOSCTRL_DANT, 0x0020100AU);
163 io_write_32(QOSCTRL_FSS, 0x0000000AU);
164 io_write_32(QOSCTRL_INSFC, 0x06330001U);
165 io_write_32(QOSCTRL_RACNT0, 0x00010003U);
166
167 /* GPU Boost Mode */
168 io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
169
170 io_write_32(QOSCTRL_SL_INIT,
171 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
172 SL_INIT_SSLOTCLK_H3_30);
173 io_write_32(QOSCTRL_REF_ARS,
174 ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3_30 << 16)));
175
176 uint32_t i;
177
178 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
179 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
180 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
181 }
182 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
183 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
184 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
185 }
186 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
187 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
188 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
189 qoswt_fix[i]);
190 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
191 qoswt_fix[i]);
192 }
193 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
194 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
195 io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
196 }
197 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
198
199 /* AXI setting */
200 io_write_32(AXI_MMCR, 0x00010008U);
201 io_write_32(AXI_TR3CR, 0x00010000U);
202 io_write_32(AXI_TR4CR, 0x00010000U);
203
204 /* RT bus Leaf setting */
205 io_write_32(RT_ACT0, 0x00000000U);
206 io_write_32(RT_ACT1, 0x00000000U);
207
208 /* CCI bus Leaf setting */
209 io_write_32(CPU_ACT0, 0x00000003U);
210 io_write_32(CPU_ACT1, 0x00000003U);
211 io_write_32(CPU_ACT2, 0x00000003U);
212 io_write_32(CPU_ACT3, 0x00000003U);
213
214 io_write_32(QOSCTRL_RAEN, 0x00000001U);
215
216 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
217 /* re-write training setting */
218 io_write_32(QOSWT_WTREF,
219 ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
220 io_write_32(QOSWT_WTSET0,
221 ((QOSWT_WTSET0_PERIOD0_H3_30 << 16) |
222 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
223 io_write_32(QOSWT_WTSET1,
224 ((QOSWT_WTSET1_PERIOD1_H3_30 << 16) |
225 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
226
227 io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
228 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
229
230 io_write_32(QOSCTRL_STATQC, 0x00000001U);
231 #else
232 NOTICE("BL2: QoS is None\n");
233
234 io_write_32(QOSCTRL_RAEN, 0x00000001U);
235 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
236 }
237