1 /*
2 * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10
11 #include "../qos_common.h"
12 #include "../qos_reg.h"
13 #include "qos_init_h3n_v30.h"
14
15 #define RCAR_QOS_VERSION "rev.0.07"
16
17 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */
18
19 #define QOSWT_WTEN_ENABLE 0x1U
20
21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N (SL_INIT_SSLOTCLK_H3N - 0x5U)
22
23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
25 #define QOSWT_WTREF_SLOT0_EN \
26 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
27 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
28 #define QOSWT_WTREF_SLOT1_EN \
29 ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
30 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
31
32 #define QOSWT_WTSET0_REQ_SSLOT0 5U
33 #define WT_BASE_SUB_SLOT_NUM0 12U
34 #define QOSWT_WTSET0_PERIOD0_H3N \
35 ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_H3N) - 1U)
36 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
37 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
38
39 #define QOSWT_WTSET1_PERIOD1_H3N (QOSWT_WTSET0_PERIOD0_H3N)
40 #define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
41 #define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
42
43 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
44
45 #if RCAR_REF_INT == RCAR_REF_DEFAULT
46 #include "qos_init_h3n_v30_mstat195.h"
47 #else
48 #include "qos_init_h3n_v30_mstat390.h"
49 #endif
50
51 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
52
53 #if RCAR_REF_INT == RCAR_REF_DEFAULT
54 #include "qos_init_h3n_v30_qoswt195.h"
55 #else
56 #include "qos_init_h3n_v30_qoswt390.h"
57 #endif
58
59 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
60
61 #endif
62
63 struct rcar_gen3_dbsc_qos_settings h3n_v30_qos[] = {
64 /* BUFCAM settings */
65 { DBSC_DBCAM0CNF1, 0x00043218U },
66 { DBSC_DBCAM0CNF2, 0x000000F4U },
67 { DBSC_DBCAM0CNF3, 0x00000000U },
68 { DBSC_DBSCHCNT0, 0x000F0037U },
69 { DBSC_DBSCHSZ0, 0x00000001U },
70 { DBSC_DBSCHRW0, 0x22421111U },
71
72 /* DDR3 */
73 { DBSC_SCFCTST2, 0x012F1123U },
74
75 /* QoS Settings */
76 { DBSC_DBSCHQOS00, 0x00000F00U },
77 { DBSC_DBSCHQOS01, 0x00000B00U },
78 { DBSC_DBSCHQOS02, 0x00000000U },
79 { DBSC_DBSCHQOS03, 0x00000000U },
80 { DBSC_DBSCHQOS40, 0x00000300U },
81 { DBSC_DBSCHQOS41, 0x000002F0U },
82 { DBSC_DBSCHQOS42, 0x00000200U },
83 { DBSC_DBSCHQOS43, 0x00000100U },
84 { DBSC_DBSCHQOS90, 0x00000100U },
85 { DBSC_DBSCHQOS91, 0x000000F0U },
86 { DBSC_DBSCHQOS92, 0x000000A0U },
87 { DBSC_DBSCHQOS93, 0x00000040U },
88 { DBSC_DBSCHQOS120, 0x00000040U },
89 { DBSC_DBSCHQOS121, 0x00000030U },
90 { DBSC_DBSCHQOS122, 0x00000020U },
91 { DBSC_DBSCHQOS123, 0x00000010U },
92 { DBSC_DBSCHQOS130, 0x00000100U },
93 { DBSC_DBSCHQOS131, 0x000000F0U },
94 { DBSC_DBSCHQOS132, 0x000000A0U },
95 { DBSC_DBSCHQOS133, 0x00000040U },
96 { DBSC_DBSCHQOS140, 0x000000C0U },
97 { DBSC_DBSCHQOS141, 0x000000B0U },
98 { DBSC_DBSCHQOS142, 0x00000080U },
99 { DBSC_DBSCHQOS143, 0x00000040U },
100 { DBSC_DBSCHQOS150, 0x00000040U },
101 { DBSC_DBSCHQOS151, 0x00000030U },
102 { DBSC_DBSCHQOS152, 0x00000020U },
103 { DBSC_DBSCHQOS153, 0x00000010U },
104 };
105
qos_init_h3n_v30(void)106 void qos_init_h3n_v30(void)
107 {
108 unsigned int split_area;
109
110 rcar_qos_dbsc_setting(h3n_v30_qos, ARRAY_SIZE(h3n_v30_qos), true);
111
112 /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
113 split_area = 0x1CU;
114
115 /* DRAM Split Address mapping */
116 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
117 #if RCAR_LSI == RCAR_H3N
118 #error "Don't set DRAM Split 4ch(H3N)"
119 #else
120 ERROR("DRAM Split 4ch not supported.(H3N)");
121 panic();
122 #endif
123 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
124 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
125 NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
126
127 io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
128 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
129 | ADSPLCR0_SPLITSEL(0xFFU)
130 | ADSPLCR0_AREA(split_area)
131 | ADSPLCR0_SWP);
132 io_write_32(AXI_ADSPLCR2, 0x00001004U);
133 io_write_32(AXI_ADSPLCR3, 0x00000000U);
134 #else
135 io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
136 NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
137 #endif
138
139 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
140 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
141 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
142 #endif
143
144 #if RCAR_REF_INT == RCAR_REF_DEFAULT
145 NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
146 #else
147 NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
148 #endif
149
150 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
151 NOTICE("BL2: Periodic Write DQ Training\n");
152 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
153
154 io_write_32(QOSCTRL_RAS, 0x00000044U);
155 io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
156 io_write_32(QOSCTRL_DANT, 0x0020100AU);
157 io_write_32(QOSCTRL_FSS, 0x0000000AU);
158 io_write_32(QOSCTRL_INSFC, 0x06330001U);
159 io_write_32(QOSCTRL_RACNT0, 0x00010003U);
160
161 /* GPU Boost Mode */
162 io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
163
164 io_write_32(QOSCTRL_SL_INIT,
165 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
166 SL_INIT_SSLOTCLK_H3N);
167 io_write_32(QOSCTRL_REF_ARS,
168 ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
169
170 uint32_t i;
171
172 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
173 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
174 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
175 }
176 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
177 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
178 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
179 }
180 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
181 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
182 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
183 qoswt_fix[i]);
184 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
185 qoswt_fix[i]);
186 }
187 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
188 io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
189 io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
190 }
191 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
192
193 /* AXI setting */
194 io_write_32(AXI_MMCR, 0x00010008U);
195 io_write_32(AXI_TR3CR, 0x00010000U);
196 io_write_32(AXI_TR4CR, 0x00010000U);
197
198 /* RT bus Leaf setting */
199 io_write_32(RT_ACT0, 0x00000000U);
200 io_write_32(RT_ACT1, 0x00000000U);
201
202 /* CCI bus Leaf setting */
203 io_write_32(CPU_ACT0, 0x00000003U);
204 io_write_32(CPU_ACT1, 0x00000003U);
205 io_write_32(CPU_ACT2, 0x00000003U);
206 io_write_32(CPU_ACT3, 0x00000003U);
207
208 io_write_32(QOSCTRL_RAEN, 0x00000001U);
209
210 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
211 /* re-write training setting */
212 io_write_32(QOSWT_WTREF,
213 ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
214 io_write_32(QOSWT_WTSET0,
215 ((QOSWT_WTSET0_PERIOD0_H3N << 16) |
216 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
217 io_write_32(QOSWT_WTSET1,
218 ((QOSWT_WTSET1_PERIOD1_H3N << 16) |
219 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
220
221 io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
222 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
223
224 io_write_32(QOSCTRL_STATQC, 0x00000001U);
225 #else
226 NOTICE("BL2: QoS is None\n");
227
228 io_write_32(QOSCTRL_RAEN, 0x00000001U);
229 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
230 }
231