1 /* 2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef QOS_COMMON_H 8 #define QOS_COMMON_H 9 10 #define RCAR_REF_DEFAULT 0U 11 12 /* define used for get_refperiod. */ 13 /* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */ 14 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */ 15 #define REFPERIOD_CYCLE /* unit:ns */ \ 16 ((126U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 17 #else /* REF option */ 18 #define REFPERIOD_CYCLE /* unit:ns */ \ 19 ((252U * BASE_SUB_SLOT_NUM * 1000U) / 400U) 20 #endif 21 22 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) 23 /* define used for G2M */ 24 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 25 #define SUB_SLOT_CYCLE_G2M_11 0x7EU /* 126 */ 26 #define SUB_SLOT_CYCLE_G2M_30 0x7EU /* 126 */ 27 #else /* REF 3.9usec */ 28 #define SUB_SLOT_CYCLE_G2M_11 0xFCU /* 252 */ 29 #define SUB_SLOT_CYCLE_G2M_30 0xFCU /* 252 */ 30 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 31 32 #define SL_INIT_SSLOTCLK_G2M_11 (SUB_SLOT_CYCLE_G2M_11 - 1U) 33 #define SL_INIT_SSLOTCLK_G2M_30 (SUB_SLOT_CYCLE_G2M_30 - 1U) 34 #define QOSWT_WTSET0_CYCLE_G2M_11 /* unit:ns */ \ 35 ((SUB_SLOT_CYCLE_G2M_11 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 36 #define QOSWT_WTSET0_CYCLE_G2M_30 /* unit:ns */ \ 37 ((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 38 #endif 39 40 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) 41 /* define used for G2N */ 42 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 43 #define SUB_SLOT_CYCLE_G2N 0x7EU /* 126 */ 44 #else /* REF 3.9usec */ 45 #define SUB_SLOT_CYCLE_G2N 0xFCU /* 252 */ 46 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 47 48 #define SL_INIT_SSLOTCLK_G2N (SUB_SLOT_CYCLE_G2N - 1U) 49 #define QOSWT_WTSET0_CYCLE_G2N /* unit:ns */ \ 50 ((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 51 #endif /* (RCAR_LSI == RZ_G2N) */ 52 53 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) 54 /* define used for G2H */ 55 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */ 56 #define SUB_SLOT_CYCLE_G2H 0x7EU /* 126 */ 57 #else /* REF 3.9usec */ 58 #define SUB_SLOT_CYCLE_G2H 0xFCU /* 252 */ 59 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 60 61 #define SL_INIT_SSLOTCLK_G2H (SUB_SLOT_CYCLE_G2H - 1U) 62 #define QOSWT_WTSET0_CYCLE_G2H /* unit:ns */ \ 63 ((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 64 #endif 65 66 #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E) 67 /* define used for G2E */ 68 #if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */ 69 #define SUB_SLOT_CYCLE_G2E 0xAFU /* 175 */ 70 #else /* REF 7.8usec */ 71 #define SUB_SLOT_CYCLE_G2E 0x15EU /* 350 */ 72 #endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */ 73 74 #define OPERATING_FREQ_G2E 266U /* MHz */ 75 #define SL_INIT_SSLOTCLK_G2E (SUB_SLOT_CYCLE_G2E - 1U) 76 #endif 77 78 #define OPERATING_FREQ 400U /* MHz */ 79 #define BASE_SUB_SLOT_NUM 0x6U 80 #define SUB_SLOT_CYCLE 0x7EU /* 126 */ 81 82 #define QOSWT_WTSET0_CYCLE /* unit:ns */ \ 83 ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) 84 85 #define SL_INIT_REFFSSLOT (0x3U << 24U) 86 #define SL_INIT_SLOTSSLOT ((BASE_SUB_SLOT_NUM - 1U) << 16U) 87 #define SL_INIT_SSLOTCLK (SUB_SLOT_CYCLE - 1U) 88 89 typedef struct { 90 uintptr_t addr; 91 uint64_t value; 92 } mstat_slot_t; 93 94 struct rcar_gen3_dbsc_qos_settings { 95 uint32_t reg; 96 uint32_t val; 97 }; 98 99 extern uint32_t qos_init_ddr_ch; 100 extern uint8_t qos_init_ddr_phyvalid; 101 102 void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos, 103 unsigned int qos_size, bool dbsc_wren); 104 105 #endif /* QOS_COMMON_H */ 106