1 /*
2 * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <limits.h>
10 #include <stdint.h>
11
12 #include <libfdt.h>
13
14 #include <platform_def.h>
15
16 #include <common/debug.h>
17 #include <drivers/delay_timer.h>
18 #include <drivers/raw_nand.h>
19 #include <drivers/st/stm32_fmc2_nand.h>
20 #include <drivers/st/stm32_gpio.h>
21 #include <drivers/st/stm32mp_reset.h>
22 #include <lib/mmio.h>
23 #include <lib/utils_def.h>
24
25 /* Timeout for device interface reset */
26 #define TIMEOUT_US_1_MS 1000U
27
28 /* FMC2 Compatibility */
29 #define DT_FMC2_EBI_COMPAT "st,stm32mp1-fmc2-ebi"
30 #define DT_FMC2_NFC_COMPAT "st,stm32mp1-fmc2-nfc"
31 #define MAX_CS 2U
32 #define MAX_BANK 5U
33
34 /* FMC2 Controller Registers */
35 #define FMC2_BCR1 0x00U
36 #define FMC2_PCR 0x80U
37 #define FMC2_SR 0x84U
38 #define FMC2_PMEM 0x88U
39 #define FMC2_PATT 0x8CU
40 #define FMC2_HECCR 0x94U
41 #define FMC2_BCHISR 0x254U
42 #define FMC2_BCHICR 0x258U
43 #define FMC2_BCHDSR0 0x27CU
44 #define FMC2_BCHDSR1 0x280U
45 #define FMC2_BCHDSR2 0x284U
46 #define FMC2_BCHDSR3 0x288U
47 #define FMC2_BCHDSR4 0x28CU
48
49 /* FMC2_BCR1 register */
50 #define FMC2_BCR1_FMC2EN BIT(31)
51 /* FMC2_PCR register */
52 #define FMC2_PCR_PWAITEN BIT(1)
53 #define FMC2_PCR_PBKEN BIT(2)
54 #define FMC2_PCR_PWID_MASK GENMASK_32(5, 4)
55 #define FMC2_PCR_PWID(x) (((x) << 4) & FMC2_PCR_PWID_MASK)
56 #define FMC2_PCR_PWID_8 0x0U
57 #define FMC2_PCR_PWID_16 0x1U
58 #define FMC2_PCR_ECCEN BIT(6)
59 #define FMC2_PCR_ECCALG BIT(8)
60 #define FMC2_PCR_TCLR_MASK GENMASK_32(12, 9)
61 #define FMC2_PCR_TCLR(x) (((x) << 9) & FMC2_PCR_TCLR_MASK)
62 #define FMC2_PCR_TCLR_DEFAULT 0xFU
63 #define FMC2_PCR_TAR_MASK GENMASK_32(16, 13)
64 #define FMC2_PCR_TAR(x) (((x) << 13) & FMC2_PCR_TAR_MASK)
65 #define FMC2_PCR_TAR_DEFAULT 0xFU
66 #define FMC2_PCR_ECCSS_MASK GENMASK_32(19, 17)
67 #define FMC2_PCR_ECCSS(x) (((x) << 17) & FMC2_PCR_ECCSS_MASK)
68 #define FMC2_PCR_ECCSS_512 0x1U
69 #define FMC2_PCR_ECCSS_2048 0x3U
70 #define FMC2_PCR_BCHECC BIT(24)
71 #define FMC2_PCR_WEN BIT(25)
72 /* FMC2_SR register */
73 #define FMC2_SR_NWRF BIT(6)
74 /* FMC2_PMEM register*/
75 #define FMC2_PMEM_MEMSET(x) (((x) & GENMASK_32(7, 0)) << 0)
76 #define FMC2_PMEM_MEMWAIT(x) (((x) & GENMASK_32(7, 0)) << 8)
77 #define FMC2_PMEM_MEMHOLD(x) (((x) & GENMASK_32(7, 0)) << 16)
78 #define FMC2_PMEM_MEMHIZ(x) (((x) & GENMASK_32(7, 0)) << 24)
79 #define FMC2_PMEM_DEFAULT 0x0A0A0A0AU
80 /* FMC2_PATT register */
81 #define FMC2_PATT_ATTSET(x) (((x) & GENMASK_32(7, 0)) << 0)
82 #define FMC2_PATT_ATTWAIT(x) (((x) & GENMASK_32(7, 0)) << 8)
83 #define FMC2_PATT_ATTHOLD(x) (((x) & GENMASK_32(7, 0)) << 16)
84 #define FMC2_PATT_ATTHIZ(x) (((x) & GENMASK_32(7, 0)) << 24)
85 #define FMC2_PATT_DEFAULT 0x0A0A0A0AU
86 /* FMC2_BCHISR register */
87 #define FMC2_BCHISR_DERF BIT(1)
88 /* FMC2_BCHICR register */
89 #define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0)
90 /* FMC2_BCHDSR0 register */
91 #define FMC2_BCHDSR0_DUE BIT(0)
92 #define FMC2_BCHDSR0_DEF BIT(1)
93 #define FMC2_BCHDSR0_DEN_MASK GENMASK_32(7, 4)
94 #define FMC2_BCHDSR0_DEN_SHIFT 4U
95 /* FMC2_BCHDSR1 register */
96 #define FMC2_BCHDSR1_EBP1_MASK GENMASK_32(12, 0)
97 #define FMC2_BCHDSR1_EBP2_MASK GENMASK_32(28, 16)
98 #define FMC2_BCHDSR1_EBP2_SHIFT 16U
99 /* FMC2_BCHDSR2 register */
100 #define FMC2_BCHDSR2_EBP3_MASK GENMASK_32(12, 0)
101 #define FMC2_BCHDSR2_EBP4_MASK GENMASK_32(28, 16)
102 #define FMC2_BCHDSR2_EBP4_SHIFT 16U
103 /* FMC2_BCHDSR3 register */
104 #define FMC2_BCHDSR3_EBP5_MASK GENMASK_32(12, 0)
105 #define FMC2_BCHDSR3_EBP6_MASK GENMASK_32(28, 16)
106 #define FMC2_BCHDSR3_EBP6_SHIFT 16U
107 /* FMC2_BCHDSR4 register */
108 #define FMC2_BCHDSR4_EBP7_MASK GENMASK_32(12, 0)
109 #define FMC2_BCHDSR4_EBP8_MASK GENMASK_32(28, 16)
110 #define FMC2_BCHDSR4_EBP8_SHIFT 16U
111
112 /* Timings */
113 #define FMC2_THIZ 0x01U
114 #define FMC2_TIO 8000U
115 #define FMC2_TSYNC 3000U
116 #define FMC2_PCR_TIMING_MASK GENMASK_32(3, 0)
117 #define FMC2_PMEM_PATT_TIMING_MASK GENMASK_32(7, 0)
118
119 #define FMC2_BBM_LEN 2U
120 #define FMC2_MAX_ECC_BYTES 14U
121 #define TIMEOUT_US_10_MS 10000U
122 #define FMC2_PSEC_PER_MSEC (1000UL * 1000UL * 1000UL)
123
124 enum stm32_fmc2_ecc {
125 FMC2_ECC_HAM = 1U,
126 FMC2_ECC_BCH4 = 4U,
127 FMC2_ECC_BCH8 = 8U
128 };
129
130 struct stm32_fmc2_cs_reg {
131 uintptr_t data_base;
132 uintptr_t cmd_base;
133 uintptr_t addr_base;
134 };
135
136 struct stm32_fmc2_nand_timings {
137 uint8_t tclr;
138 uint8_t tar;
139 uint8_t thiz;
140 uint8_t twait;
141 uint8_t thold_mem;
142 uint8_t tset_mem;
143 uint8_t thold_att;
144 uint8_t tset_att;
145 };
146
147 struct stm32_fmc2_nfc {
148 uintptr_t reg_base;
149 struct stm32_fmc2_cs_reg cs[MAX_CS];
150 unsigned long clock_id;
151 unsigned int reset_id;
152 uint8_t cs_sel;
153 };
154
155 static struct stm32_fmc2_nfc stm32_fmc2;
156
fmc2_base(void)157 static uintptr_t fmc2_base(void)
158 {
159 return stm32_fmc2.reg_base;
160 }
161
stm32_fmc2_nand_setup_timing(void)162 static void stm32_fmc2_nand_setup_timing(void)
163 {
164 struct stm32_fmc2_nand_timings tims;
165 unsigned long hclk = stm32mp_clk_get_rate(stm32_fmc2.clock_id);
166 unsigned long hclkp = FMC2_PSEC_PER_MSEC / (hclk / 1000U);
167 unsigned long timing, tar, tclr, thiz, twait;
168 unsigned long tset_mem, tset_att, thold_mem, thold_att;
169 uint32_t pcr, pmem, patt;
170
171 tar = MAX(hclkp, NAND_TAR_MIN);
172 timing = div_round_up(tar, hclkp) - 1U;
173 tims.tar = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK);
174
175 tclr = MAX(hclkp, NAND_TCLR_MIN);
176 timing = div_round_up(tclr, hclkp) - 1U;
177 tims.tclr = MIN(timing, (unsigned long)FMC2_PCR_TIMING_MASK);
178
179 tims.thiz = FMC2_THIZ;
180 thiz = (tims.thiz + 1U) * hclkp;
181
182 /*
183 * tWAIT > tRP
184 * tWAIT > tWP
185 * tWAIT > tREA + tIO
186 */
187 twait = MAX(hclkp, NAND_TRP_MIN);
188 twait = MAX(twait, NAND_TWP_MIN);
189 twait = MAX(twait, NAND_TREA_MAX + FMC2_TIO);
190 timing = div_round_up(twait, hclkp);
191 tims.twait = CLAMP(timing, 1UL,
192 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
193
194 /*
195 * tSETUP_MEM > tCS - tWAIT
196 * tSETUP_MEM > tALS - tWAIT
197 * tSETUP_MEM > tDS - (tWAIT - tHIZ)
198 */
199 tset_mem = hclkp;
200 if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) {
201 tset_mem = NAND_TCS_MIN - twait;
202 }
203 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) &&
204 (tset_mem < (NAND_TDS_MIN - (twait - thiz)))) {
205 tset_mem = NAND_TDS_MIN - (twait - thiz);
206 }
207 timing = div_round_up(tset_mem, hclkp);
208 tims.tset_mem = CLAMP(timing, 1UL,
209 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
210
211 /*
212 * tHOLD_MEM > tCH
213 * tHOLD_MEM > tREH - tSETUP_MEM
214 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT)
215 */
216 thold_mem = MAX(hclkp, NAND_TCH_MIN);
217 if ((tset_mem < NAND_TREH_MIN) &&
218 (thold_mem < (NAND_TREH_MIN - tset_mem))) {
219 thold_mem = NAND_TREH_MIN - tset_mem;
220 }
221 if (((tset_mem + twait) < NAND_TRC_MIN) &&
222 (thold_mem < (NAND_TRC_MIN - (tset_mem + twait)))) {
223 thold_mem = NAND_TRC_MIN - (tset_mem + twait);
224 }
225 if (((tset_mem + twait) < NAND_TWC_MIN) &&
226 (thold_mem < (NAND_TWC_MIN - (tset_mem + twait)))) {
227 thold_mem = NAND_TWC_MIN - (tset_mem + twait);
228 }
229 timing = div_round_up(thold_mem, hclkp);
230 tims.thold_mem = CLAMP(timing, 1UL,
231 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
232
233 /*
234 * tSETUP_ATT > tCS - tWAIT
235 * tSETUP_ATT > tCLS - tWAIT
236 * tSETUP_ATT > tALS - tWAIT
237 * tSETUP_ATT > tRHW - tHOLD_MEM
238 * tSETUP_ATT > tDS - (tWAIT - tHIZ)
239 */
240 tset_att = hclkp;
241 if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) {
242 tset_att = NAND_TCS_MIN - twait;
243 }
244 if ((thold_mem < NAND_TRHW_MIN) &&
245 (tset_att < (NAND_TRHW_MIN - thold_mem))) {
246 tset_att = NAND_TRHW_MIN - thold_mem;
247 }
248 if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) &&
249 (tset_att < (NAND_TDS_MIN - (twait - thiz)))) {
250 tset_att = NAND_TDS_MIN - (twait - thiz);
251 }
252 timing = div_round_up(tset_att, hclkp);
253 tims.tset_att = CLAMP(timing, 1UL,
254 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
255
256 /*
257 * tHOLD_ATT > tALH
258 * tHOLD_ATT > tCH
259 * tHOLD_ATT > tCLH
260 * tHOLD_ATT > tCOH
261 * tHOLD_ATT > tDH
262 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM
263 * tHOLD_ATT > tADL - tSETUP_MEM
264 * tHOLD_ATT > tWH - tSETUP_MEM
265 * tHOLD_ATT > tWHR - tSETUP_MEM
266 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT)
267 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT)
268 */
269 thold_att = MAX(hclkp, NAND_TALH_MIN);
270 thold_att = MAX(thold_att, NAND_TCH_MIN);
271 thold_att = MAX(thold_att, NAND_TCLH_MIN);
272 thold_att = MAX(thold_att, NAND_TCOH_MIN);
273 thold_att = MAX(thold_att, NAND_TDH_MIN);
274 if (((NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC) > tset_mem) &&
275 (thold_att < (NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem))) {
276 thold_att = NAND_TWB_MAX + FMC2_TIO + FMC2_TSYNC - tset_mem;
277 }
278 if ((tset_mem < NAND_TADL_MIN) &&
279 (thold_att < (NAND_TADL_MIN - tset_mem))) {
280 thold_att = NAND_TADL_MIN - tset_mem;
281 }
282 if ((tset_mem < NAND_TWH_MIN) &&
283 (thold_att < (NAND_TWH_MIN - tset_mem))) {
284 thold_att = NAND_TWH_MIN - tset_mem;
285 }
286 if ((tset_mem < NAND_TWHR_MIN) &&
287 (thold_att < (NAND_TWHR_MIN - tset_mem))) {
288 thold_att = NAND_TWHR_MIN - tset_mem;
289 }
290 if (((tset_att + twait) < NAND_TRC_MIN) &&
291 (thold_att < (NAND_TRC_MIN - (tset_att + twait)))) {
292 thold_att = NAND_TRC_MIN - (tset_att + twait);
293 }
294 if (((tset_att + twait) < NAND_TWC_MIN) &&
295 (thold_att < (NAND_TWC_MIN - (tset_att + twait)))) {
296 thold_att = NAND_TWC_MIN - (tset_att + twait);
297 }
298 timing = div_round_up(thold_att, hclkp);
299 tims.thold_att = CLAMP(timing, 1UL,
300 (unsigned long)FMC2_PMEM_PATT_TIMING_MASK);
301
302 VERBOSE("NAND timings: %u - %u - %u - %u - %u - %u - %u - %u\n",
303 tims.tclr, tims.tar, tims.thiz, tims.twait,
304 tims.thold_mem, tims.tset_mem,
305 tims.thold_att, tims.tset_att);
306
307 /* Set tclr/tar timings */
308 pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
309 pcr &= ~FMC2_PCR_TCLR_MASK;
310 pcr |= FMC2_PCR_TCLR(tims.tclr);
311 pcr &= ~FMC2_PCR_TAR_MASK;
312 pcr |= FMC2_PCR_TAR(tims.tar);
313
314 /* Set tset/twait/thold/thiz timings in common bank */
315 pmem = FMC2_PMEM_MEMSET(tims.tset_mem);
316 pmem |= FMC2_PMEM_MEMWAIT(tims.twait);
317 pmem |= FMC2_PMEM_MEMHOLD(tims.thold_mem);
318 pmem |= FMC2_PMEM_MEMHIZ(tims.thiz);
319
320 /* Set tset/twait/thold/thiz timings in attribute bank */
321 patt = FMC2_PATT_ATTSET(tims.tset_att);
322 patt |= FMC2_PATT_ATTWAIT(tims.twait);
323 patt |= FMC2_PATT_ATTHOLD(tims.thold_att);
324 patt |= FMC2_PATT_ATTHIZ(tims.thiz);
325
326 mmio_write_32(fmc2_base() + FMC2_PCR, pcr);
327 mmio_write_32(fmc2_base() + FMC2_PMEM, pmem);
328 mmio_write_32(fmc2_base() + FMC2_PATT, patt);
329 }
330
stm32_fmc2_set_buswidth_16(bool set)331 static void stm32_fmc2_set_buswidth_16(bool set)
332 {
333 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_PWID_MASK,
334 (set ? FMC2_PCR_PWID(FMC2_PCR_PWID_16) : 0U));
335 }
336
stm32_fmc2_set_ecc(bool enable)337 static void stm32_fmc2_set_ecc(bool enable)
338 {
339 mmio_clrsetbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_ECCEN,
340 (enable ? FMC2_PCR_ECCEN : 0U));
341 }
342
stm32_fmc2_ham_correct(uint8_t * buffer,uint8_t * eccbuffer,uint8_t * ecc)343 static int stm32_fmc2_ham_correct(uint8_t *buffer, uint8_t *eccbuffer,
344 uint8_t *ecc)
345 {
346 uint8_t xor_ecc_ones;
347 uint16_t xor_ecc_1b, xor_ecc_2b, xor_ecc_3b;
348 union {
349 uint32_t val;
350 uint8_t bytes[4];
351 } xor_ecc;
352
353 /* Page size--------ECC_Code Size
354 * 256---------------22 bits LSB (ECC_CODE & 0x003FFFFF)
355 * 512---------------24 bits (ECC_CODE & 0x00FFFFFF)
356 * 1024--------------26 bits (ECC_CODE & 0x03FFFFFF)
357 * 2048--------------28 bits (ECC_CODE & 0x0FFFFFFF)
358 * 4096--------------30 bits (ECC_CODE & 0x3FFFFFFF)
359 * 8192--------------32 bits (ECC_CODE & 0xFFFFFFFF)
360 */
361
362 /* For Page size 512, ECC_Code size 24 bits */
363 xor_ecc_1b = ecc[0] ^ eccbuffer[0];
364 xor_ecc_2b = ecc[1] ^ eccbuffer[1];
365 xor_ecc_3b = ecc[2] ^ eccbuffer[2];
366
367 xor_ecc.val = 0U;
368 xor_ecc.bytes[2] = xor_ecc_3b;
369 xor_ecc.bytes[1] = xor_ecc_2b;
370 xor_ecc.bytes[0] = xor_ecc_1b;
371
372 if (xor_ecc.val == 0U) {
373 return 0; /* No Error */
374 }
375
376 xor_ecc_ones = __builtin_popcount(xor_ecc.val);
377 if (xor_ecc_ones < 23U) {
378 if (xor_ecc_ones == 12U) {
379 uint16_t bit_address, byte_address;
380
381 /* Correctable ERROR */
382 bit_address = ((xor_ecc_1b >> 1) & BIT(0)) |
383 ((xor_ecc_1b >> 2) & BIT(1)) |
384 ((xor_ecc_1b >> 3) & BIT(2));
385
386 byte_address = ((xor_ecc_1b >> 7) & BIT(0)) |
387 ((xor_ecc_2b) & BIT(1)) |
388 ((xor_ecc_2b >> 1) & BIT(2)) |
389 ((xor_ecc_2b >> 2) & BIT(3)) |
390 ((xor_ecc_2b >> 3) & BIT(4)) |
391 ((xor_ecc_3b << 4) & BIT(5)) |
392 ((xor_ecc_3b << 3) & BIT(6)) |
393 ((xor_ecc_3b << 2) & BIT(7)) |
394 ((xor_ecc_3b << 1) & BIT(8));
395
396 /* Correct bit error in the data */
397 buffer[byte_address] =
398 buffer[byte_address] ^ BIT(bit_address);
399 VERBOSE("Hamming: 1 ECC error corrected\n");
400
401 return 0;
402 }
403
404 /* Non Correctable ERROR */
405 ERROR("%s: Uncorrectable ECC Errors\n", __func__);
406 return -1;
407 }
408
409 /* ECC ERROR */
410 ERROR("%s: Hamming correction error\n", __func__);
411 return -1;
412 }
413
414
stm32_fmc2_ham_calculate(uint8_t * buffer,uint8_t * ecc)415 static int stm32_fmc2_ham_calculate(uint8_t *buffer, uint8_t *ecc)
416 {
417 uint32_t heccr;
418 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS);
419
420 while ((mmio_read_32(fmc2_base() + FMC2_SR) & FMC2_SR_NWRF) == 0U) {
421 if (timeout_elapsed(timeout)) {
422 return -ETIMEDOUT;
423 }
424 }
425
426 heccr = mmio_read_32(fmc2_base() + FMC2_HECCR);
427
428 ecc[0] = heccr;
429 ecc[1] = heccr >> 8;
430 ecc[2] = heccr >> 16;
431
432 /* Disable ECC */
433 stm32_fmc2_set_ecc(false);
434
435 return 0;
436 }
437
stm32_fmc2_bch_correct(uint8_t * buffer,unsigned int eccsize)438 static int stm32_fmc2_bch_correct(uint8_t *buffer, unsigned int eccsize)
439 {
440 uint32_t bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4;
441 uint16_t pos[8];
442 int i, den;
443 uint64_t timeout = timeout_init_us(TIMEOUT_US_10_MS);
444
445 while ((mmio_read_32(fmc2_base() + FMC2_BCHISR) &
446 FMC2_BCHISR_DERF) == 0U) {
447 if (timeout_elapsed(timeout)) {
448 return -ETIMEDOUT;
449 }
450 }
451
452 bchdsr0 = mmio_read_32(fmc2_base() + FMC2_BCHDSR0);
453 bchdsr1 = mmio_read_32(fmc2_base() + FMC2_BCHDSR1);
454 bchdsr2 = mmio_read_32(fmc2_base() + FMC2_BCHDSR2);
455 bchdsr3 = mmio_read_32(fmc2_base() + FMC2_BCHDSR3);
456 bchdsr4 = mmio_read_32(fmc2_base() + FMC2_BCHDSR4);
457
458 /* Disable ECC */
459 stm32_fmc2_set_ecc(false);
460
461 /* No error found */
462 if ((bchdsr0 & FMC2_BCHDSR0_DEF) == 0U) {
463 return 0;
464 }
465
466 /* Too many errors detected */
467 if ((bchdsr0 & FMC2_BCHDSR0_DUE) != 0U) {
468 return -EBADMSG;
469 }
470
471 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK;
472 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT;
473 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK;
474 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT;
475 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK;
476 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT;
477 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK;
478 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT;
479
480 den = (bchdsr0 & FMC2_BCHDSR0_DEN_MASK) >> FMC2_BCHDSR0_DEN_SHIFT;
481 for (i = 0; i < den; i++) {
482 if (pos[i] < (eccsize * 8U)) {
483 uint8_t bitmask = BIT(pos[i] % 8U);
484 uint32_t offset = pos[i] / 8U;
485
486 *(buffer + offset) ^= bitmask;
487 }
488 }
489
490 return 0;
491 }
492
stm32_fmc2_hwctl(struct nand_device * nand)493 static void stm32_fmc2_hwctl(struct nand_device *nand)
494 {
495 stm32_fmc2_set_ecc(false);
496
497 if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) {
498 mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN);
499 mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ);
500 }
501
502 stm32_fmc2_set_ecc(true);
503 }
504
stm32_fmc2_read_page(struct nand_device * nand,unsigned int page,uintptr_t buffer)505 static int stm32_fmc2_read_page(struct nand_device *nand,
506 unsigned int page, uintptr_t buffer)
507 {
508 unsigned int eccsize = nand->ecc.size;
509 unsigned int eccbytes = nand->ecc.bytes;
510 unsigned int eccsteps = nand->page_size / eccsize;
511 uint8_t ecc_corr[FMC2_MAX_ECC_BYTES];
512 uint8_t ecc_cal[FMC2_MAX_ECC_BYTES] = {0U};
513 uint8_t *p;
514 unsigned int i;
515 unsigned int s;
516 int ret;
517
518 VERBOSE(">%s page %i buffer %lx\n", __func__, page, buffer);
519
520 ret = nand_read_page_cmd(page, 0U, 0U, 0U);
521 if (ret != 0) {
522 return ret;
523 }
524
525 for (s = 0U, i = nand->page_size + FMC2_BBM_LEN, p = (uint8_t *)buffer;
526 s < eccsteps;
527 s++, i += eccbytes, p += eccsize) {
528 stm32_fmc2_hwctl(nand);
529
530 /* Read the NAND page sector (512 bytes) */
531 ret = nand_change_read_column_cmd(s * eccsize, (uintptr_t)p,
532 eccsize);
533 if (ret != 0) {
534 return ret;
535 }
536
537 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) {
538 ret = stm32_fmc2_ham_calculate(p, ecc_cal);
539 if (ret != 0) {
540 return ret;
541 }
542 }
543
544 /* Read the corresponding ECC bytes */
545 ret = nand_change_read_column_cmd(i, (uintptr_t)ecc_corr,
546 eccbytes);
547 if (ret != 0) {
548 return ret;
549 }
550
551 /* Correct the data */
552 if (nand->ecc.max_bit_corr == FMC2_ECC_HAM) {
553 ret = stm32_fmc2_ham_correct(p, ecc_corr, ecc_cal);
554 } else {
555 ret = stm32_fmc2_bch_correct(p, eccsize);
556 }
557
558 if (ret != 0) {
559 return ret;
560 }
561 }
562
563 return 0;
564 }
565
stm32_fmc2_read_data(struct nand_device * nand,uint8_t * buff,unsigned int length,bool use_bus8)566 static void stm32_fmc2_read_data(struct nand_device *nand,
567 uint8_t *buff, unsigned int length,
568 bool use_bus8)
569 {
570 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;
571
572 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
573 stm32_fmc2_set_buswidth_16(false);
574 }
575
576 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) {
577 *buff = mmio_read_8(data_base);
578 buff += sizeof(uint8_t);
579 length -= sizeof(uint8_t);
580 }
581
582 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) &&
583 (length >= sizeof(uint16_t))) {
584 *(uint16_t *)buff = mmio_read_16(data_base);
585 buff += sizeof(uint16_t);
586 length -= sizeof(uint16_t);
587 }
588
589 /* 32bit aligned */
590 while (length >= sizeof(uint32_t)) {
591 *(uint32_t *)buff = mmio_read_32(data_base);
592 buff += sizeof(uint32_t);
593 length -= sizeof(uint32_t);
594 }
595
596 /* Read remaining bytes */
597 if (length >= sizeof(uint16_t)) {
598 *(uint16_t *)buff = mmio_read_16(data_base);
599 buff += sizeof(uint16_t);
600 length -= sizeof(uint16_t);
601 }
602
603 if (length != 0U) {
604 *buff = mmio_read_8(data_base);
605 }
606
607 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
608 /* Reconfigure bus width to 16-bit */
609 stm32_fmc2_set_buswidth_16(true);
610 }
611 }
612
stm32_fmc2_write_data(struct nand_device * nand,uint8_t * buff,unsigned int length,bool use_bus8)613 static void stm32_fmc2_write_data(struct nand_device *nand,
614 uint8_t *buff, unsigned int length,
615 bool use_bus8)
616 {
617 uintptr_t data_base = stm32_fmc2.cs[stm32_fmc2.cs_sel].data_base;
618
619 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
620 /* Reconfigure bus width to 8-bit */
621 stm32_fmc2_set_buswidth_16(false);
622 }
623
624 if ((((uintptr_t)buff & BIT(0)) != 0U) && (length != 0U)) {
625 mmio_write_8(data_base, *buff);
626 buff += sizeof(uint8_t);
627 length -= sizeof(uint8_t);
628 }
629
630 if ((((uintptr_t)buff & GENMASK_32(1, 0)) != 0U) &&
631 (length >= sizeof(uint16_t))) {
632 mmio_write_16(data_base, *(uint16_t *)buff);
633 buff += sizeof(uint16_t);
634 length -= sizeof(uint16_t);
635 }
636
637 /* 32bits aligned */
638 while (length >= sizeof(uint32_t)) {
639 mmio_write_32(data_base, *(uint32_t *)buff);
640 buff += sizeof(uint32_t);
641 length -= sizeof(uint32_t);
642 }
643
644 /* Read remaining bytes */
645 if (length >= sizeof(uint16_t)) {
646 mmio_write_16(data_base, *(uint16_t *)buff);
647 buff += sizeof(uint16_t);
648 length -= sizeof(uint16_t);
649 }
650
651 if (length != 0U) {
652 mmio_write_8(data_base, *buff);
653 }
654
655 if (use_bus8 && (nand->buswidth == NAND_BUS_WIDTH_16)) {
656 /* Reconfigure bus width to 16-bit */
657 stm32_fmc2_set_buswidth_16(true);
658 }
659 }
660
stm32_fmc2_ctrl_init(void)661 static void stm32_fmc2_ctrl_init(void)
662 {
663 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
664 uint32_t bcr1 = mmio_read_32(fmc2_base() + FMC2_BCR1);
665
666 /* Enable wait feature and NAND flash memory bank */
667 pcr |= FMC2_PCR_PWAITEN;
668 pcr |= FMC2_PCR_PBKEN;
669
670 /* Set buswidth to 8 bits mode for identification */
671 pcr &= ~FMC2_PCR_PWID_MASK;
672
673 /* ECC logic is disabled */
674 pcr &= ~FMC2_PCR_ECCEN;
675
676 /* Default mode */
677 pcr &= ~FMC2_PCR_ECCALG;
678 pcr &= ~FMC2_PCR_BCHECC;
679 pcr &= ~FMC2_PCR_WEN;
680
681 /* Set default ECC sector size */
682 pcr &= ~FMC2_PCR_ECCSS_MASK;
683 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_2048);
684
685 /* Set default TCLR/TAR timings */
686 pcr &= ~FMC2_PCR_TCLR_MASK;
687 pcr |= FMC2_PCR_TCLR(FMC2_PCR_TCLR_DEFAULT);
688 pcr &= ~FMC2_PCR_TAR_MASK;
689 pcr |= FMC2_PCR_TAR(FMC2_PCR_TAR_DEFAULT);
690
691 /* Enable FMC2 controller */
692 bcr1 |= FMC2_BCR1_FMC2EN;
693
694 mmio_write_32(fmc2_base() + FMC2_BCR1, bcr1);
695 mmio_write_32(fmc2_base() + FMC2_PCR, pcr);
696 mmio_write_32(fmc2_base() + FMC2_PMEM, FMC2_PMEM_DEFAULT);
697 mmio_write_32(fmc2_base() + FMC2_PATT, FMC2_PATT_DEFAULT);
698 }
699
stm32_fmc2_exec(struct nand_req * req)700 static int stm32_fmc2_exec(struct nand_req *req)
701 {
702 int ret = 0;
703
704 switch (req->type & NAND_REQ_MASK) {
705 case NAND_REQ_CMD:
706 VERBOSE("Write CMD %x\n", (uint8_t)req->type);
707 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].cmd_base,
708 (uint8_t)req->type);
709 break;
710 case NAND_REQ_ADDR:
711 VERBOSE("Write ADDR %x\n", *(req->addr));
712 mmio_write_8(stm32_fmc2.cs[stm32_fmc2.cs_sel].addr_base,
713 *(req->addr));
714 break;
715 case NAND_REQ_DATAIN:
716 VERBOSE("Read data\n");
717 stm32_fmc2_read_data(req->nand, req->addr, req->length,
718 ((req->type & NAND_REQ_BUS_WIDTH_8) !=
719 0U));
720 break;
721 case NAND_REQ_DATAOUT:
722 VERBOSE("Write data\n");
723 stm32_fmc2_write_data(req->nand, req->addr, req->length,
724 ((req->type & NAND_REQ_BUS_WIDTH_8) !=
725 0U));
726 break;
727 case NAND_REQ_WAIT:
728 VERBOSE("WAIT Ready\n");
729 ret = nand_wait_ready(req->delay_ms);
730 break;
731 default:
732 ret = -EINVAL;
733 break;
734 };
735
736 return ret;
737 }
738
stm32_fmc2_setup(struct nand_device * nand)739 static void stm32_fmc2_setup(struct nand_device *nand)
740 {
741 uint32_t pcr = mmio_read_32(fmc2_base() + FMC2_PCR);
742
743 /* Set buswidth */
744 pcr &= ~FMC2_PCR_PWID_MASK;
745 if (nand->buswidth == NAND_BUS_WIDTH_16) {
746 pcr |= FMC2_PCR_PWID(FMC2_PCR_PWID_16);
747 }
748
749 if (nand->ecc.mode == NAND_ECC_HW) {
750 nand->mtd_read_page = stm32_fmc2_read_page;
751
752 pcr &= ~FMC2_PCR_ECCALG;
753 pcr &= ~FMC2_PCR_BCHECC;
754
755 pcr &= ~FMC2_PCR_ECCSS_MASK;
756 pcr |= FMC2_PCR_ECCSS(FMC2_PCR_ECCSS_512);
757
758 switch (nand->ecc.max_bit_corr) {
759 case FMC2_ECC_HAM:
760 nand->ecc.bytes = 3;
761 break;
762 case FMC2_ECC_BCH8:
763 pcr |= FMC2_PCR_ECCALG;
764 pcr |= FMC2_PCR_BCHECC;
765 nand->ecc.bytes = 13;
766 break;
767 default:
768 /* Use FMC2 ECC BCH4 */
769 pcr |= FMC2_PCR_ECCALG;
770 nand->ecc.bytes = 7;
771 break;
772 }
773
774 if ((nand->buswidth & NAND_BUS_WIDTH_16) != 0) {
775 nand->ecc.bytes++;
776 }
777 }
778
779 mmio_write_32(stm32_fmc2.reg_base + FMC2_PCR, pcr);
780 }
781
782 static const struct nand_ctrl_ops ctrl_ops = {
783 .setup = stm32_fmc2_setup,
784 .exec = stm32_fmc2_exec
785 };
786
stm32_fmc2_init(void)787 int stm32_fmc2_init(void)
788 {
789 int fmc_ebi_node;
790 int fmc_nfc_node;
791 int fmc_flash_node = 0;
792 int nchips = 0;
793 unsigned int i;
794 void *fdt = NULL;
795 const fdt32_t *cuint;
796 struct dt_node_info info;
797 uintptr_t bank_address[MAX_BANK] = { 0, 0, 0, 0, 0 };
798 uint8_t bank_assigned = 0;
799 uint8_t bank;
800 int ret;
801
802 if (fdt_get_address(&fdt) == 0) {
803 return -FDT_ERR_NOTFOUND;
804 }
805
806 fmc_ebi_node = dt_get_node(&info, -1, DT_FMC2_EBI_COMPAT);
807 if (fmc_ebi_node < 0) {
808 return fmc_ebi_node;
809 }
810
811 if (info.status == DT_DISABLED) {
812 return -FDT_ERR_NOTFOUND;
813 }
814
815 stm32_fmc2.reg_base = info.base;
816
817 if ((info.clock < 0) || (info.reset < 0)) {
818 return -FDT_ERR_BADVALUE;
819 }
820
821 stm32_fmc2.clock_id = (unsigned long)info.clock;
822 stm32_fmc2.reset_id = (unsigned int)info.reset;
823
824 cuint = fdt_getprop(fdt, fmc_ebi_node, "ranges", NULL);
825 if (cuint == NULL) {
826 return -FDT_ERR_BADVALUE;
827 }
828
829 for (i = 0U; i < MAX_BANK; i++) {
830 bank = fdt32_to_cpu(*cuint);
831 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) {
832 return -FDT_ERR_BADVALUE;
833 }
834 bank_assigned |= BIT(bank);
835 bank_address[bank] = fdt32_to_cpu(*(cuint + 2));
836 cuint += 4;
837 }
838
839 /* Pinctrl initialization */
840 if (dt_set_pinctrl_config(fmc_ebi_node) != 0) {
841 return -FDT_ERR_BADVALUE;
842 }
843
844 /* Parse NFC controller node */
845 fmc_nfc_node = fdt_node_offset_by_compatible(fdt, fmc_ebi_node,
846 DT_FMC2_NFC_COMPAT);
847 if (fmc_nfc_node < 0) {
848 return fmc_nfc_node;
849 }
850
851 if (fdt_get_status(fmc_nfc_node) == DT_DISABLED) {
852 return -FDT_ERR_NOTFOUND;
853 }
854
855 cuint = fdt_getprop(fdt, fmc_nfc_node, "reg", NULL);
856 if (cuint == NULL) {
857 return -FDT_ERR_BADVALUE;
858 }
859
860 for (i = 0U; i < MAX_CS; i++) {
861 bank = fdt32_to_cpu(*cuint);
862 if (bank >= MAX_BANK) {
863 return -FDT_ERR_BADVALUE;
864 }
865 stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) +
866 bank_address[bank];
867
868 bank = fdt32_to_cpu(*(cuint + 3));
869 if (bank >= MAX_BANK) {
870 return -FDT_ERR_BADVALUE;
871 }
872 stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) +
873 bank_address[bank];
874
875 bank = fdt32_to_cpu(*(cuint + 6));
876 if (bank >= MAX_BANK) {
877 return -FDT_ERR_BADVALUE;
878 }
879 stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) +
880 bank_address[bank];
881
882 cuint += 9;
883 }
884
885 /* Parse flash nodes */
886 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) {
887 nchips++;
888 }
889
890 if (nchips != 1) {
891 WARN("Only one SLC NAND device supported\n");
892 return -FDT_ERR_BADVALUE;
893 }
894
895 fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) {
896 /* Get chip select */
897 cuint = fdt_getprop(fdt, fmc_flash_node, "reg", NULL);
898 if (cuint == NULL) {
899 WARN("Chip select not well defined\n");
900 return -FDT_ERR_BADVALUE;
901 }
902
903 stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint);
904 if (stm32_fmc2.cs_sel >= MAX_CS) {
905 return -FDT_ERR_BADVALUE;
906 }
907
908 VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel);
909 }
910
911 /* Enable Clock */
912 stm32mp_clk_enable(stm32_fmc2.clock_id);
913
914 /* Reset IP */
915 ret = stm32mp_reset_assert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);
916 if (ret != 0) {
917 panic();
918 }
919 ret = stm32mp_reset_deassert(stm32_fmc2.reset_id, TIMEOUT_US_1_MS);
920 if (ret != 0) {
921 panic();
922 }
923
924 /* Setup default IP registers */
925 stm32_fmc2_ctrl_init();
926
927 /* Setup default timings */
928 stm32_fmc2_nand_setup_timing();
929
930 /* Init NAND RAW framework */
931 nand_raw_ctrl_init(&ctrl_ops);
932
933 return 0;
934 }
935