1/*
2 * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8
9/ {
10	model = "A5DS";
11	compatible = "arm,A5DS";
12	interrupt-parent = <&gic>;
13	#address-cells = <1>;
14	#size-cells = <1>;
15
16	psci {
17		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
18		method = "smc";
19		cpu_on = <0x84000003>;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25		enable-method = "psci";
26		cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a5";
29			reg = <0>;
30			next-level-cache = <&L2>;
31		};
32		cpu@1 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a5";
35			reg = <1>;
36			next-level-cache = <&L2>;
37		};
38		cpu@2 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a5";
41			reg = <2>;
42			next-level-cache = <&L2>;
43		};
44		cpu@3 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a5";
47			reg = <3>;
48			next-level-cache = <&L2>;
49		};
50	};
51
52	memory@80000000 {
53		device_type = "memory";
54		reg = <0x80000000 0x7F000000>;
55	};
56
57	L2: cache-controller@1C010000 {
58		compatible = "arm,pl310-cache";
59		reg = <0x1C010000 0x1000>;
60		interrupts = <0 84 4>;
61		cache-level = <2>;
62		cache-unified;
63		arm,data-latency = <1 1 1>;
64		arm,tag-latency = <1 1 1>;
65	};
66
67	refclk7500khz: refclk7500khz {
68		compatible = "fixed-clock";
69		#clock-cells = <0>;
70		clock-frequency = <7500000>;
71		clock-output-names = "apb_pclk";
72	};
73
74	refclk24mhz: refclk24mhz {
75		compatible = "fixed-clock";
76		#clock-cells = <0>;
77		clock-frequency = <24000000>;
78		clock-output-names = "apb_pclk";
79	};
80
81	smbclk: refclk24mhzx2 {
82		compatible = "fixed-clock";
83		#clock-cells = <0>;
84		clock-frequency = <48000000>;
85		clock-output-names = "smclk";
86	};
87
88
89	rtc@1a220000 {
90		compatible = "arm,pl031", "arm,primecell";
91		reg = <0x1a220000 0x1000>;
92		clocks = <&refclk24mhz>;
93		interrupts = <0 6 0xf04>;
94		clock-names = "apb_pclk";
95	};
96
97	gic: interrupt-controller@1c001000 {
98		compatible = "arm,cortex-a9-gic";
99		#interrupt-cells = <3>;
100		#address-cells = <0>;
101		interrupt-controller;
102		reg = <0x1c001000 0x1000>,
103			  <0x1c000100 0x100>;
104		interrupts = <1 9 0xf04>;
105	};
106
107	serial0: uart@1a200000 {
108		compatible = "arm,pl011", "arm,primecell";
109		reg = <0x1a200000 0x1000>;
110		interrupt-parent = <&gic>;
111		interrupts = <0 8 0xf04>;
112		clocks = <&refclk7500khz>;
113		clock-names = "apb_pclk";
114	};
115
116	serial1: uart@1a210000 {
117		compatible = "arm,pl011", "arm,primecell";
118		reg = <0x1a210000 0x1000>;
119		interrupt-parent = <&gic>;
120		interrupts = <0 9 0xf04>;
121		clocks = <&refclk7500khz>;
122		clock-names = "apb_pclk";
123	};
124
125	timer0: timer@1a040000 {
126		compatible = "arm,armv7-timer-mem";
127		#address-cells = <1>;
128		#size-cells = <1>;
129		ranges;
130		reg = <0x1a040000 0x1000>;
131		clock-frequency = <7500000>;
132
133		frame@1a050000 {
134			frame-number = <0>;
135			interrupts = <0 2 0xf04>;
136			reg = <0x1a050000 0x1000>;
137		};
138	};
139	v2m_fixed_3v3: fixed-regulator-0 {
140		compatible = "regulator-fixed";
141		regulator-name = "3V3";
142		regulator-min-microvolt = <3300000>;
143		regulator-max-microvolt = <3300000>;
144		regulator-always-on;
145	};
146
147	ethernet@4020000 {
148		compatible = "smsc,lan9220", "smsc,lan9115";
149		reg = <0x40200000 0x10000>;
150		interrupt-parent = <&gic>;
151		interrupts = <0 43 0xf04>;
152		reg-io-width = <4>;
153		phy-mode = "mii";
154		smsc,irq-active-high;
155		vdd33a-supply = <&v2m_fixed_3v3>;
156		vddvario-supply = <&v2m_fixed_3v3>;
157       };
158};
159