1// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
2/*
3 * Copyright (c) 2020, Arm Limited. All rights reserved.
4 *
5 * Devicetree for the Arm Ltd. FPGA platform
6 * Number and kind of CPU cores differs from image to image, so the
7 * topology is auto-detected by BL31, and the /cpus node is created and
8 * populated accordingly at runtime.
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/dts-v1/;
14
15/ {
16	model = "ARM FPGA";
17	compatible = "arm,fpga", "arm,vexpress";
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		serial0 = &dbg_uart;
24	};
25
26	chosen {
27		stdout-path = "serial0:38400n8";
28		bootargs = "console=ttyAMA0,38400n8 earlycon";
29		/* Allow to upload a generous 100MB initrd payload. */
30		linux,initrd-start = <0x0 0x84000000>;
31		linux,initrd-end = <0x0 0x8a400000>;
32	};
33
34	/* /cpus node will be added by BL31 at runtime. */
35
36	psci {
37		compatible = "arm,psci-0.2";
38		method = "smc";
39	};
40
41	timer {
42		compatible = "arm,armv8-timer";
43		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
44			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
45			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
46			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
47	};
48
49	pmu {
50		compatible = "arm,armv8-pmuv3";
51		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
52	};
53
54	/* This node will be removed at runtime on cores without SPE. */
55	spe-pmu {
56		compatible = "arm,statistical-profiling-extension-v1";
57		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
58	};
59
60	memory@80000000 {
61		device_type = "memory";
62		reg = <0x0 0x80000000 0x0 0x80000000>,
63		      <0x8 0x80000000 0x1 0x80000000>;
64	};
65
66
67	bus_refclk: refclk {
68		compatible = "fixed-clock";
69		#clock-cells = <0>;
70		clock-frequency = <100000000>;
71		clock-output-names = "apb_pclk";
72	};
73
74	uartclk: baudclock {
75		compatible = "fixed-clock";
76		#clock-cells = <0>;
77		clock-frequency = <10000000>;
78		clock-output-names = "uartclk";
79	};
80
81	dbg_uart: serial@7ff80000 {
82		compatible = "arm,pl011", "arm,primecell";
83		reg = <0x0 0x7ff80000 0x0 0x00001000>;
84		interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
85		clocks = <&uartclk>, <&bus_refclk>;
86		clock-names = "uartclk", "apb_pclk";
87	};
88
89	gic: interrupt-controller@30000000 {
90		compatible = "arm,gic-v3";
91		#address-cells = <2>;
92		#interrupt-cells = <3>;
93		#size-cells = <2>;
94		ranges;
95		interrupt-controller;
96		reg = <0x0 0x30000000 0x0 0x00010000>,	/* GICD */
97	/* The GICR size will be adjusted at runtime to match the cores. */
98		      <0x0 0x30040000 0x0 0x00020000>;	/* GICR for one core */
99		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
100
101		its: msi-controller@30040000 {
102			compatible = "arm,gic-v3-its";
103			reg = <0x0 0x30040000 0x0 0x40000>;
104			#msi-cells = <1>;
105			msi-controller;
106		};
107	};
108};
109