1/*
2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12};
13
14/ {
15	model = "FVP Base";
16	compatible = "arm,vfp-base", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	aliases {
24		serial0 = &v2m_serial0;
25		serial1 = &v2m_serial1;
26		serial2 = &v2m_serial2;
27		serial3 = &v2m_serial3;
28	};
29
30	psci {
31		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
32		method = "smc";
33		cpu_suspend = <0x84000001>;
34		cpu_off = <0x84000002>;
35		cpu_on = <0x84000003>;
36		sys_poweroff = <0x84000008>;
37		sys_reset = <0x84000009>;
38		max-pwr-lvl = <2>;
39	};
40
41	cpus {
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		CPU_MAP
46
47		idle-states {
48			entry-method = "arm,psci";
49
50			CPU_SLEEP_0: cpu-sleep-0 {
51				compatible = "arm,idle-state";
52				local-timer-stop;
53				arm,psci-suspend-param = <0x0010000>;
54				entry-latency-us = <40>;
55				exit-latency-us = <100>;
56				min-residency-us = <150>;
57			};
58
59			CLUSTER_SLEEP_0: cluster-sleep-0 {
60				compatible = "arm,idle-state";
61				local-timer-stop;
62				arm,psci-suspend-param = <0x1010000>;
63				entry-latency-us = <500>;
64				exit-latency-us = <1000>;
65				min-residency-us = <2500>;
66			};
67		};
68
69		CPUS
70
71		L2_0: l2-cache0 {
72			compatible = "cache";
73		};
74	};
75
76	memory@80000000 {
77		device_type = "memory";
78		reg = <0x00000000 0x80000000 0 0x7F000000>,
79		      <0x00000008 0x80000000 0 0x80000000>;
80	};
81
82	gic: interrupt-controller@2f000000 {
83		compatible = "arm,gic-v3";
84		#interrupt-cells = <3>;
85		#address-cells = <2>;
86		#size-cells = <2>;
87		ranges;
88		interrupt-controller;
89		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
90		      <0x0 0x2f100000 0 0x200000>,	// GICR
91		      <0x0 0x2c000000 0 0x2000>,	// GICC
92		      <0x0 0x2c010000 0 0x2000>,	// GICH
93		      <0x0 0x2c02f000 0 0x2000>;	// GICV
94		interrupts = <1 9 4>;
95
96		its: its@2f020000 {
97			compatible = "arm,gic-v3-its";
98			msi-controller;
99			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
100		};
101	};
102
103	timer {
104		compatible = "arm,armv8-timer";
105		interrupts = <GIC_PPI 13
106				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
107			     <GIC_PPI 14
108				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
109			     <GIC_PPI 11
110				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
111			     <GIC_PPI 10
112				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
113		clock-frequency = <100000000>;
114	};
115
116	timer@2a810000 {
117			compatible = "arm,armv7-timer-mem";
118			reg = <0x0 0x2a810000 0x0 0x10000>;
119			clock-frequency = <100000000>;
120			#address-cells = <2>;
121			#size-cells = <2>;
122			ranges;
123			frame@2a830000 {
124				frame-number = <1>;
125				interrupts = <0 26 4>;
126				reg = <0x0 0x2a830000 0x0 0x10000>;
127			};
128	};
129
130	pmu {
131		compatible = "arm,armv8-pmuv3";
132		interrupts = <0 60 4>,
133			     <0 61 4>,
134			     <0 62 4>,
135			     <0 63 4>;
136	};
137
138	smb {
139		compatible = "simple-bus";
140
141		#address-cells = <2>;
142		#size-cells = <1>;
143		ranges = <0 0 0 0x08000000 0x04000000>,
144			 <1 0 0 0x14000000 0x04000000>,
145			 <2 0 0 0x18000000 0x04000000>,
146			 <3 0 0 0x1c000000 0x04000000>,
147			 <4 0 0 0x0c000000 0x04000000>,
148			 <5 0 0 0x10000000 0x04000000>;
149
150		#interrupt-cells = <1>;
151		interrupt-map-mask = <0 0 63>;
152		interrupt-map = <0 0  0 &gic 0 0 0  0 4>,
153				<0 0  1 &gic 0 0 0  1 4>,
154				<0 0  2 &gic 0 0 0  2 4>,
155				<0 0  3 &gic 0 0 0  3 4>,
156				<0 0  4 &gic 0 0 0  4 4>,
157				<0 0  5 &gic 0 0 0  5 4>,
158				<0 0  6 &gic 0 0 0  6 4>,
159				<0 0  7 &gic 0 0 0  7 4>,
160				<0 0  8 &gic 0 0 0  8 4>,
161				<0 0  9 &gic 0 0 0  9 4>,
162				<0 0 10 &gic 0 0 0 10 4>,
163				<0 0 11 &gic 0 0 0 11 4>,
164				<0 0 12 &gic 0 0 0 12 4>,
165				<0 0 13 &gic 0 0 0 13 4>,
166				<0 0 14 &gic 0 0 0 14 4>,
167				<0 0 15 &gic 0 0 0 15 4>,
168				<0 0 16 &gic 0 0 0 16 4>,
169				<0 0 17 &gic 0 0 0 17 4>,
170				<0 0 18 &gic 0 0 0 18 4>,
171				<0 0 19 &gic 0 0 0 19 4>,
172				<0 0 20 &gic 0 0 0 20 4>,
173				<0 0 21 &gic 0 0 0 21 4>,
174				<0 0 22 &gic 0 0 0 22 4>,
175				<0 0 23 &gic 0 0 0 23 4>,
176				<0 0 24 &gic 0 0 0 24 4>,
177				<0 0 25 &gic 0 0 0 25 4>,
178				<0 0 26 &gic 0 0 0 26 4>,
179				<0 0 27 &gic 0 0 0 27 4>,
180				<0 0 28 &gic 0 0 0 28 4>,
181				<0 0 29 &gic 0 0 0 29 4>,
182				<0 0 30 &gic 0 0 0 30 4>,
183				<0 0 31 &gic 0 0 0 31 4>,
184				<0 0 32 &gic 0 0 0 32 4>,
185				<0 0 33 &gic 0 0 0 33 4>,
186				<0 0 34 &gic 0 0 0 34 4>,
187				<0 0 35 &gic 0 0 0 35 4>,
188				<0 0 36 &gic 0 0 0 36 4>,
189				<0 0 37 &gic 0 0 0 37 4>,
190				<0 0 38 &gic 0 0 0 38 4>,
191				<0 0 39 &gic 0 0 0 39 4>,
192				<0 0 40 &gic 0 0 0 40 4>,
193				<0 0 41 &gic 0 0 0 41 4>,
194				<0 0 42 &gic 0 0 0 42 4>;
195
196		#include "rtsm_ve-motherboard-aarch32.dtsi"
197	};
198
199	panels {
200		panel@0 {
201			compatible	= "panel";
202			mode		= "XVGA";
203			refresh		= <60>;
204			xres		= <1024>;
205			yres		= <768>;
206			pixclock	= <15748>;
207			left_margin	= <152>;
208			right_margin	= <48>;
209			upper_margin	= <23>;
210			lower_margin	= <3>;
211			hsync_len	= <104>;
212			vsync_len	= <4>;
213			sync		= <0>;
214			vmode		= "FB_VMODE_NONINTERLACED";
215			tim2		= "TIM2_BCD", "TIM2_IPC";
216			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
217			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
218			bpp		= <16>;
219		};
220	};
221};
222