1/*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <services/sdei_flags.h>
9
10#define LEVEL	0
11#define EDGE	2
12#define SDEI_NORMAL	0x70
13#define HIGHEST_SEC	0
14
15/memreserve/ 0x80000000 0x00010000;
16
17/ {
18};
19
20/ {
21	model = "FVP Base";
22	compatible = "arm,vfp-base", "arm,vexpress";
23	interrupt-parent = <&gic>;
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27#if (ENABLE_RME == 1)
28	chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";};
29#else
30	chosen {};
31#endif
32
33	aliases {
34		serial0 = &v2m_serial0;
35		serial1 = &v2m_serial1;
36		serial2 = &v2m_serial2;
37		serial3 = &v2m_serial3;
38	};
39
40	psci {
41		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
42		method = "smc";
43		cpu_suspend = <0xc4000001>;
44		cpu_off = <0x84000002>;
45		cpu_on = <0xc4000003>;
46		sys_poweroff = <0x84000008>;
47		sys_reset = <0x84000009>;
48		max-pwr-lvl = <2>;
49	};
50
51#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
52	firmware {
53#if SDEI_IN_FCONF
54		sdei {
55			compatible = "arm,sdei-1.0";
56			method = "smc";
57			private_event_count = <3>;
58			shared_event_count = <3>;
59			/*
60			 * Each event descriptor has typically 3 fields:
61			 * 1. Event number
62			 * 2. Interrupt number the event is bound to or
63			 *    if event is dynamic, specified as SDEI_DYN_IRQ
64			 * 3. Bit map of event flags
65			 */
66			private_events =	<1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
67						<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
68						<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
69			shared_events =		<2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
70						<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
71						<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
72		};
73#endif /* SDEI_IN_FCONF */
74
75#if SEC_INT_DESC_IN_FCONF
76		sec_interrupts {
77			compatible = "arm,secure_interrupt_desc";
78			/* Number of G0 and G1 secure interrupts defined by the platform */
79			g0_intr_cnt = <2>;
80			g1s_intr_cnt = <9>;
81			/*
82			 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
83			 * terminology. Each interrupt property descriptor has 3 fields:
84			 * 1. Interrupt number
85			 * 2. Interrupt priority
86			 * 3. Type of interrupt (Edge or Level configured)
87			 */
88			g0_intr_desc =	< 8 SDEI_NORMAL EDGE>,
89					<14 HIGHEST_SEC EDGE>;
90
91			g1s_intr_desc =	< 9 HIGHEST_SEC EDGE>,
92					<10 HIGHEST_SEC EDGE>,
93					<11 HIGHEST_SEC EDGE>,
94					<12 HIGHEST_SEC EDGE>,
95					<13 HIGHEST_SEC EDGE>,
96					<15 HIGHEST_SEC EDGE>,
97					<29 HIGHEST_SEC LEVEL>,
98					<56 HIGHEST_SEC LEVEL>,
99					<57 HIGHEST_SEC LEVEL>;
100		};
101#endif /* SEC_INT_DESC_IN_FCONF */
102	};
103#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */
104
105	cpus {
106		#address-cells = <2>;
107		#size-cells = <0>;
108
109		CPU_MAP
110
111		idle-states {
112			entry-method = "arm,psci";
113
114			CPU_SLEEP_0: cpu-sleep-0 {
115				compatible = "arm,idle-state";
116				local-timer-stop;
117				arm,psci-suspend-param = <0x0010000>;
118				entry-latency-us = <40>;
119				exit-latency-us = <100>;
120				min-residency-us = <150>;
121			};
122
123			CLUSTER_SLEEP_0: cluster-sleep-0 {
124				compatible = "arm,idle-state";
125				local-timer-stop;
126				arm,psci-suspend-param = <0x1010000>;
127				entry-latency-us = <500>;
128				exit-latency-us = <1000>;
129				min-residency-us = <2500>;
130			};
131		};
132
133		CPUS
134
135		L2_0: l2-cache0 {
136			compatible = "cache";
137		};
138	};
139
140	memory@80000000 {
141		device_type = "memory";
142#if (ENABLE_RME == 1)
143		reg = <0x00000000 0x80000000 0 0x7C000000>,
144		      <0x00000008 0x80000000 0 0x80000000>;
145#else
146		reg = <0x00000000 0x80000000 0 0x7F000000>,
147		      <0x00000008 0x80000000 0 0x80000000>;
148#endif
149	};
150
151	gic: interrupt-controller@2f000000 {
152		compatible = "arm,gic-v3";
153		#interrupt-cells = <3>;
154		#address-cells = <2>;
155		#size-cells = <2>;
156		ranges;
157		interrupt-controller;
158		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
159		      <0x0 0x2f100000 0 0x200000>,	// GICR
160		      <0x0 0x2c000000 0 0x2000>,	// GICC
161		      <0x0 0x2c010000 0 0x2000>,	// GICH
162		      <0x0 0x2c02f000 0 0x2000>;	// GICV
163		interrupts = <1 9 4>;
164
165		its: its@2f020000 {
166			compatible = "arm,gic-v3-its";
167			msi-controller;
168			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
169		};
170	};
171
172	timer {
173		compatible = "arm,armv8-timer";
174		interrupts = <GIC_PPI 13
175				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
176			     <GIC_PPI 14
177				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
178			     <GIC_PPI 11
179				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
180			     <GIC_PPI 10
181				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
182		clock-frequency = <100000000>;
183	};
184
185	timer@2a810000 {
186			compatible = "arm,armv7-timer-mem";
187			reg = <0x0 0x2a810000 0x0 0x10000>;
188			clock-frequency = <100000000>;
189			#address-cells = <2>;
190			#size-cells = <2>;
191			ranges;
192			frame@2a830000 {
193				frame-number = <1>;
194				interrupts = <0 26 4>;
195				reg = <0x0 0x2a830000 0x0 0x10000>;
196			};
197	};
198
199	pmu {
200		compatible = "arm,armv8-pmuv3";
201		interrupts = <0 60 4>,
202			     <0 61 4>,
203			     <0 62 4>,
204			     <0 63 4>;
205	};
206
207	smb@0,0 {
208		compatible = "simple-bus";
209
210		#address-cells = <2>;
211		#size-cells = <1>;
212		ranges = <0 0 0 0x08000000 0x04000000>,
213			 <1 0 0 0x14000000 0x04000000>,
214			 <2 0 0 0x18000000 0x04000000>,
215			 <3 0 0 0x1c000000 0x04000000>,
216			 <4 0 0 0x0c000000 0x04000000>,
217			 <5 0 0 0x10000000 0x04000000>;
218
219		#include "rtsm_ve-motherboard.dtsi"
220	};
221
222	panels {
223		panel {
224			compatible	= "panel";
225			mode		= "XVGA";
226			refresh		= <60>;
227			xres		= <1024>;
228			yres		= <768>;
229			pixclock	= <15748>;
230			left_margin	= <152>;
231			right_margin	= <48>;
232			upper_margin	= <23>;
233			lower_margin	= <3>;
234			hsync_len	= <104>;
235			vsync_len	= <4>;
236			sync		= <0>;
237			vmode		= "FB_VMODE_NONINTERLACED";
238			tim2		= "TIM2_BCD", "TIM2_IPC";
239			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
240			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
241			bpp		= <16>;
242		};
243	};
244};
245