1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp1-clksrc.h>
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	memory@c0000000 {
12		device_type = "memory";
13		reg = <0xc0000000 0x20000000>;
14	};
15
16	vin: vin {
17		compatible = "regulator-fixed";
18		regulator-name = "vin";
19		regulator-min-microvolt = <5000000>;
20		regulator-max-microvolt = <5000000>;
21		regulator-always-on;
22	};
23};
24
25&bsec {
26	board_id: board_id@ec {
27		reg = <0xec 0x4>;
28		st,non-secure-otp;
29	};
30};
31
32&clk_hse {
33	st,digbypass;
34};
35
36&cpu0{
37	cpu-supply = <&vddcore>;
38};
39
40&cpu1{
41	cpu-supply = <&vddcore>;
42};
43
44&hash1 {
45	status = "okay";
46};
47
48&i2c4 {
49	pinctrl-names = "default";
50	pinctrl-0 = <&i2c4_pins_a>;
51	i2c-scl-rising-time-ns = <185>;
52	i2c-scl-falling-time-ns = <20>;
53	clock-frequency = <400000>;
54	status = "okay";
55
56	pmic: stpmic@33 {
57		compatible = "st,stpmic1";
58		reg = <0x33>;
59		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
60		interrupt-controller;
61		#interrupt-cells = <2>;
62		status = "okay";
63
64		regulators {
65			compatible = "st,stpmic1-regulators";
66			buck1-supply = <&vin>;
67			buck2-supply = <&vin>;
68			buck3-supply = <&vin>;
69			buck4-supply = <&vin>;
70			ldo1-supply = <&v3v3>;
71			ldo2-supply = <&vin>;
72			ldo3-supply = <&vdd_ddr>;
73			ldo4-supply = <&vin>;
74			ldo5-supply = <&vin>;
75			ldo6-supply = <&v3v3>;
76			vref_ddr-supply = <&vin>;
77			boost-supply = <&vin>;
78			pwr_sw1-supply = <&bst_out>;
79			pwr_sw2-supply = <&bst_out>;
80
81			vddcore: buck1 {
82				regulator-name = "vddcore";
83				regulator-min-microvolt = <1200000>;
84				regulator-max-microvolt = <1350000>;
85				regulator-always-on;
86				regulator-initial-mode = <0>;
87				regulator-over-current-protection;
88			};
89
90			vdd_ddr: buck2 {
91				regulator-name = "vdd_ddr";
92				regulator-min-microvolt = <1350000>;
93				regulator-max-microvolt = <1350000>;
94				regulator-always-on;
95				regulator-initial-mode = <0>;
96				regulator-over-current-protection;
97			};
98
99			vdd: buck3 {
100				regulator-name = "vdd";
101				regulator-min-microvolt = <3300000>;
102				regulator-max-microvolt = <3300000>;
103				regulator-always-on;
104				st,mask-reset;
105				regulator-initial-mode = <0>;
106				regulator-over-current-protection;
107			};
108
109			v3v3: buck4 {
110				regulator-name = "v3v3";
111				regulator-min-microvolt = <3300000>;
112				regulator-max-microvolt = <3300000>;
113				regulator-always-on;
114				regulator-over-current-protection;
115				regulator-initial-mode = <0>;
116			};
117
118			v1v8_audio: ldo1 {
119				regulator-name = "v1v8_audio";
120				regulator-min-microvolt = <1800000>;
121				regulator-max-microvolt = <1800000>;
122				regulator-always-on;
123			};
124
125			v3v3_hdmi: ldo2 {
126				regulator-name = "v3v3_hdmi";
127				regulator-min-microvolt = <3300000>;
128				regulator-max-microvolt = <3300000>;
129				regulator-always-on;
130			};
131
132			vtt_ddr: ldo3 {
133				regulator-name = "vtt_ddr";
134				regulator-min-microvolt = <500000>;
135				regulator-max-microvolt = <750000>;
136				regulator-always-on;
137				regulator-over-current-protection;
138			};
139
140			vdd_usb: ldo4 {
141				regulator-name = "vdd_usb";
142				regulator-min-microvolt = <3300000>;
143				regulator-max-microvolt = <3300000>;
144			};
145
146			vdda: ldo5 {
147				regulator-name = "vdda";
148				regulator-min-microvolt = <2900000>;
149				regulator-max-microvolt = <2900000>;
150				regulator-boot-on;
151			};
152
153			v1v2_hdmi: ldo6 {
154				regulator-name = "v1v2_hdmi";
155				regulator-min-microvolt = <1200000>;
156				regulator-max-microvolt = <1200000>;
157				regulator-always-on;
158			};
159
160			vref_ddr: vref_ddr {
161				regulator-name = "vref_ddr";
162				regulator-always-on;
163				regulator-over-current-protection;
164			};
165
166			bst_out: boost {
167				regulator-name = "bst_out";
168			};
169
170			vbus_otg: pwr_sw1 {
171				regulator-name = "vbus_otg";
172			};
173
174			vbus_sw: pwr_sw2 {
175				regulator-name = "vbus_sw";
176				regulator-active-discharge = <1>;
177			};
178		};
179	};
180};
181
182&iwdg2 {
183	timeout-sec = <32>;
184	status = "okay";
185	secure-status = "okay";
186};
187
188&pwr_regulators {
189	vdd-supply = <&vdd>;
190	vdd_3v3_usbfs-supply = <&vdd_usb>;
191};
192
193&rcc {
194	secure-status = "disabled";
195	st,clksrc = <
196		CLK_MPU_PLL1P
197		CLK_AXI_PLL2P
198		CLK_MCU_PLL3P
199		CLK_PLL12_HSE
200		CLK_PLL3_HSE
201		CLK_PLL4_HSE
202		CLK_RTC_LSE
203		CLK_MCO1_DISABLED
204		CLK_MCO2_DISABLED
205	>;
206
207	st,clkdiv = <
208		1 /*MPU*/
209		0 /*AXI*/
210		0 /*MCU*/
211		1 /*APB1*/
212		1 /*APB2*/
213		1 /*APB3*/
214		1 /*APB4*/
215		2 /*APB5*/
216		23 /*RTC*/
217		0 /*MCO1*/
218		0 /*MCO2*/
219	>;
220
221	st,pkcs = <
222		CLK_CKPER_HSE
223		CLK_FMC_ACLK
224		CLK_QSPI_ACLK
225		CLK_ETH_PLL4P
226		CLK_SDMMC12_PLL4P
227		CLK_DSI_DSIPLL
228		CLK_STGEN_HSE
229		CLK_USBPHY_HSE
230		CLK_SPI2S1_PLL3Q
231		CLK_SPI2S23_PLL3Q
232		CLK_SPI45_HSI
233		CLK_SPI6_HSI
234		CLK_I2C46_HSI
235		CLK_SDMMC3_PLL4P
236		CLK_USBO_USBPHY
237		CLK_ADC_CKPER
238		CLK_CEC_LSE
239		CLK_I2C12_HSI
240		CLK_I2C35_HSI
241		CLK_UART1_HSI
242		CLK_UART24_HSI
243		CLK_UART35_HSI
244		CLK_UART6_HSI
245		CLK_UART78_HSI
246		CLK_SPDIF_PLL4P
247		CLK_FDCAN_PLL4R
248		CLK_SAI1_PLL3Q
249		CLK_SAI2_PLL3Q
250		CLK_SAI3_PLL3Q
251		CLK_SAI4_PLL3Q
252		CLK_RNG1_LSI
253		CLK_RNG2_LSI
254		CLK_LPTIM1_PCLK1
255		CLK_LPTIM23_PCLK3
256		CLK_LPTIM45_LSE
257	>;
258
259	/* VCO = 1300.0 MHz => P = 650 (CPU) */
260	pll1: st,pll@0 {
261		compatible = "st,stm32mp1-pll";
262		reg = <0>;
263		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
264		frac = < 0x800 >;
265	};
266
267	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
268	pll2: st,pll@1 {
269		compatible = "st,stm32mp1-pll";
270		reg = <1>;
271		cfg = <2 65 1 0 0 PQR(1,1,1)>;
272		frac = <0x1400>;
273	};
274
275	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
276	pll3: st,pll@2 {
277		compatible = "st,stm32mp1-pll";
278		reg = <2>;
279		cfg = <1 33 1 16 36 PQR(1,1,1)>;
280		frac = <0x1a04>;
281	};
282
283	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
284	pll4: st,pll@3 {
285		compatible = "st,stm32mp1-pll";
286		reg = <3>;
287		cfg = <3 98 5 7 7 PQR(1,1,1)>;
288	};
289};
290
291&rng1 {
292	status = "okay";
293};
294
295&rtc {
296	status = "okay";
297};
298
299&sdmmc1 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&sdmmc1_b4_pins_a>;
302	disable-wp;
303	st,neg-edge;
304	bus-width = <4>;
305	vmmc-supply = <&v3v3>;
306	status = "okay";
307};
308
309&timers15 {
310	secure-status = "okay";
311};
312
313&uart4 {
314	pinctrl-names = "default";
315	pinctrl-0 = <&uart4_pins_a>;
316	status = "okay";
317};
318
319&uart7 {
320	pinctrl-names = "default";
321	pinctrl-0 = <&uart7_pins_c>;
322	status = "disabled";
323};
324
325&usart3 {
326	pinctrl-names = "default";
327	pinctrl-0 = <&usart3_pins_c>;
328	uart-has-rtscts;
329	status = "disabled";
330};
331
332&usbotg_hs {
333	phys = <&usbphyc_port1 0>;
334	phy-names = "usb2-phy";
335	usb-role-switch;
336	status = "okay";
337};
338
339&usbphyc {
340	status = "okay";
341};
342
343&usbphyc_port0 {
344	phy-supply = <&vdd_usb>;
345};
346
347&usbphyc_port1 {
348	phy-supply = <&vdd_usb>;
349};
350