1 /* 2 * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BL_COMMON_LD_H 8 #define BL_COMMON_LD_H 9 10 #include <platform_def.h> 11 12 #ifdef __aarch64__ 13 #define STRUCT_ALIGN 8 14 #define BSS_ALIGN 16 15 #else 16 #define STRUCT_ALIGN 4 17 #define BSS_ALIGN 8 18 #endif 19 20 #ifndef DATA_ALIGN 21 #define DATA_ALIGN 1 22 #endif 23 24 #define CPU_OPS \ 25 . = ALIGN(STRUCT_ALIGN); \ 26 __CPU_OPS_START__ = .; \ 27 KEEP(*(cpu_ops)) \ 28 __CPU_OPS_END__ = .; 29 30 #define PARSER_LIB_DESCS \ 31 . = ALIGN(STRUCT_ALIGN); \ 32 __PARSER_LIB_DESCS_START__ = .; \ 33 KEEP(*(.img_parser_lib_descs)) \ 34 __PARSER_LIB_DESCS_END__ = .; 35 36 #define RT_SVC_DESCS \ 37 . = ALIGN(STRUCT_ALIGN); \ 38 __RT_SVC_DESCS_START__ = .; \ 39 KEEP(*(rt_svc_descs)) \ 40 __RT_SVC_DESCS_END__ = .; 41 42 #define PMF_SVC_DESCS \ 43 . = ALIGN(STRUCT_ALIGN); \ 44 __PMF_SVC_DESCS_START__ = .; \ 45 KEEP(*(pmf_svc_descs)) \ 46 __PMF_SVC_DESCS_END__ = .; 47 48 #define FCONF_POPULATOR \ 49 . = ALIGN(STRUCT_ALIGN); \ 50 __FCONF_POPULATOR_START__ = .; \ 51 KEEP(*(.fconf_populator)) \ 52 __FCONF_POPULATOR_END__ = .; 53 54 /* 55 * Keep the .got section in the RO section as it is patched prior to enabling 56 * the MMU and having the .got in RO is better for security. GOT is a table of 57 * addresses so ensure pointer size alignment. 58 */ 59 #define GOT \ 60 . = ALIGN(STRUCT_ALIGN); \ 61 __GOT_START__ = .; \ 62 *(.got) \ 63 __GOT_END__ = .; 64 65 /* 66 * The base xlat table 67 * 68 * It is put into the rodata section if PLAT_RO_XLAT_TABLES=1, 69 * or into the bss section otherwise. 70 */ 71 #define BASE_XLAT_TABLE \ 72 . = ALIGN(16); \ 73 *(base_xlat_table) 74 75 #if PLAT_RO_XLAT_TABLES 76 #define BASE_XLAT_TABLE_RO BASE_XLAT_TABLE 77 #define BASE_XLAT_TABLE_BSS 78 #else 79 #define BASE_XLAT_TABLE_RO 80 #define BASE_XLAT_TABLE_BSS BASE_XLAT_TABLE 81 #endif 82 83 #define RODATA_COMMON \ 84 RT_SVC_DESCS \ 85 FCONF_POPULATOR \ 86 PMF_SVC_DESCS \ 87 PARSER_LIB_DESCS \ 88 CPU_OPS \ 89 GOT \ 90 BASE_XLAT_TABLE_RO 91 92 /* 93 * .data must be placed at a lower address than the stacks if the stack 94 * protector is enabled. Alternatively, the .data.stack_protector_canary 95 * section can be placed independently of the main .data section. 96 */ 97 #define DATA_SECTION \ 98 .data . : ALIGN(DATA_ALIGN) { \ 99 __DATA_START__ = .; \ 100 *(SORT_BY_ALIGNMENT(.data*)) \ 101 __DATA_END__ = .; \ 102 } 103 104 /* 105 * .rela.dyn needs to come after .data for the read-elf utility to parse 106 * this section correctly. 107 */ 108 #if __aarch64__ 109 #define RELA_DYN_NAME .rela.dyn 110 #define RELOC_SECTIONS_PATTERN *(.rela*) 111 #else 112 #define RELA_DYN_NAME .rel.dyn 113 #define RELOC_SECTIONS_PATTERN *(.rel*) 114 #endif 115 116 #define RELA_SECTION \ 117 RELA_DYN_NAME : ALIGN(STRUCT_ALIGN) { \ 118 __RELA_START__ = .; \ 119 RELOC_SECTIONS_PATTERN \ 120 __RELA_END__ = .; \ 121 } 122 123 #if !(defined(IMAGE_BL31) && RECLAIM_INIT_CODE) 124 #define STACK_SECTION \ 125 stacks (NOLOAD) : { \ 126 __STACKS_START__ = .; \ 127 *(tzfw_normal_stacks) \ 128 __STACKS_END__ = .; \ 129 } 130 #endif 131 132 /* 133 * If BL doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__ 134 * will be zero. For this reason, the only two valid values for 135 * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value 136 * PLAT_PERCPU_BAKERY_LOCK_SIZE. 137 */ 138 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 139 #define BAKERY_LOCK_SIZE_CHECK \ 140 ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || \ 141 (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \ 142 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 143 #else 144 #define BAKERY_LOCK_SIZE_CHECK 145 #endif 146 147 /* 148 * Bakery locks are stored in normal .bss memory 149 * 150 * Each lock's data is spread across multiple cache lines, one per CPU, 151 * but multiple locks can share the same cache line. 152 * The compiler will allocate enough memory for one CPU's bakery locks, 153 * the remaining cache lines are allocated by the linker script 154 */ 155 #if !USE_COHERENT_MEM 156 #define BAKERY_LOCK_NORMAL \ 157 . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 158 __BAKERY_LOCK_START__ = .; \ 159 __PERCPU_BAKERY_LOCK_START__ = .; \ 160 *(bakery_lock) \ 161 . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 162 __PERCPU_BAKERY_LOCK_END__ = .; \ 163 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); \ 164 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ 165 __BAKERY_LOCK_END__ = .; \ 166 BAKERY_LOCK_SIZE_CHECK 167 #else 168 #define BAKERY_LOCK_NORMAL 169 #endif 170 171 /* 172 * Time-stamps are stored in normal .bss memory 173 * 174 * The compiler will allocate enough memory for one CPU's time-stamps, 175 * the remaining memory for other CPUs is allocated by the 176 * linker script 177 */ 178 #define PMF_TIMESTAMP \ 179 . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 180 __PMF_TIMESTAMP_START__ = .; \ 181 KEEP(*(pmf_timestamp_array)) \ 182 . = ALIGN(CACHE_WRITEBACK_GRANULE); \ 183 __PMF_PERCPU_TIMESTAMP_END__ = .; \ 184 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); \ 185 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); \ 186 __PMF_TIMESTAMP_END__ = .; 187 188 189 /* 190 * The .bss section gets initialised to 0 at runtime. 191 * Its base address has bigger alignment for better performance of the 192 * zero-initialization code. 193 */ 194 #define BSS_SECTION \ 195 .bss (NOLOAD) : ALIGN(BSS_ALIGN) { \ 196 __BSS_START__ = .; \ 197 *(SORT_BY_ALIGNMENT(.bss*)) \ 198 *(COMMON) \ 199 BAKERY_LOCK_NORMAL \ 200 PMF_TIMESTAMP \ 201 BASE_XLAT_TABLE_BSS \ 202 __BSS_END__ = .; \ 203 } 204 205 /* 206 * The xlat_table section is for full, aligned page tables (4K). 207 * Removing them from .bss avoids forcing 4K alignment on 208 * the .bss section. The tables are initialized to zero by the translation 209 * tables library. 210 */ 211 #define XLAT_TABLE_SECTION \ 212 xlat_table (NOLOAD) : { \ 213 *(xlat_table) \ 214 } 215 216 #endif /* BL_COMMON_LD_H */ 217