1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef GICV3_H
8 #define GICV3_H
9
10 /*******************************************************************************
11 * GICv3 and 3.1 miscellaneous definitions
12 ******************************************************************************/
13 /* Interrupt group definitions */
14 #define INTR_GROUP1S U(0)
15 #define INTR_GROUP0 U(1)
16 #define INTR_GROUP1NS U(2)
17
18 /* Interrupt IDs reported by the HPPIR and IAR registers */
19 #define PENDING_G1S_INTID U(1020)
20 #define PENDING_G1NS_INTID U(1021)
21
22 /* Constant to categorize LPI interrupt */
23 #define MIN_LPI_ID U(8192)
24
25 /* GICv3 can only target up to 16 PEs with SGI */
26 #define GICV3_MAX_SGI_TARGETS U(16)
27
28 /* PPIs INTIDs 16-31 */
29 #define MAX_PPI_ID U(31)
30
31 #if GIC_EXT_INTID
32
33 /* GICv3.1 extended PPIs INTIDs 1056-1119 */
34 #define MIN_EPPI_ID U(1056)
35 #define MAX_EPPI_ID U(1119)
36
37 /* Total number of GICv3.1 EPPIs */
38 #define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1))
39
40 /* Total number of GICv3.1 PPIs and EPPIs */
41 #define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM)
42
43 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */
44 #define MIN_ESPI_ID U(4096)
45 #define MAX_ESPI_ID U(5119)
46
47 /* Total number of GICv3.1 ESPIs */
48 #define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1))
49
50 /* Total number of GICv3.1 SPIs and ESPIs */
51 #define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM)
52
53 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
54 #define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \
55 (((id) >= MIN_EPPI_ID) && \
56 ((id) <= MAX_EPPI_ID)))
57
58 /* SPIs: 32-1019, ESPIs: 4096-5119 */
59 #define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \
60 ((id) <= MAX_SPI_ID)) || \
61 (((id) >= MIN_ESPI_ID) && \
62 ((id) <= MAX_ESPI_ID)))
63 #else /* GICv3 */
64
65 /* Total number of GICv3 PPIs */
66 #define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM
67
68 /* Total number of GICv3 SPIs */
69 #define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM
70
71 /* SGIs: 0-15, PPIs: 16-31 */
72 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID)
73
74 /* SPIs: 32-1019 */
75 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID))
76
77 #endif /* GIC_EXT_INTID */
78
79 /*******************************************************************************
80 * GICv3 and 3.1 specific Distributor interface register offsets and constants
81 ******************************************************************************/
82 #define GICD_TYPER2 U(0x0c)
83 #define GICD_STATUSR U(0x10)
84 #define GICD_SETSPI_NSR U(0x40)
85 #define GICD_CLRSPI_NSR U(0x48)
86 #define GICD_SETSPI_SR U(0x50)
87 #define GICD_CLRSPI_SR U(0x58)
88 #define GICD_IGRPMODR U(0xd00)
89 #define GICD_IGROUPRE U(0x1000)
90 #define GICD_ISENABLERE U(0x1200)
91 #define GICD_ICENABLERE U(0x1400)
92 #define GICD_ISPENDRE U(0x1600)
93 #define GICD_ICPENDRE U(0x1800)
94 #define GICD_ISACTIVERE U(0x1a00)
95 #define GICD_ICACTIVERE U(0x1c00)
96 #define GICD_IPRIORITYRE U(0x2000)
97 #define GICD_ICFGRE U(0x3000)
98 #define GICD_IGRPMODRE U(0x3400)
99 #define GICD_NSACRE U(0x3600)
100 /*
101 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID
102 * and n >= 32, making the effective offset as 0x6100
103 */
104 #define GICD_IROUTER U(0x6000)
105 #define GICD_IROUTERE U(0x8000)
106
107 #define GICD_PIDR0_GICV3 U(0xffe0)
108 #define GICD_PIDR1_GICV3 U(0xffe4)
109 #define GICD_PIDR2_GICV3 U(0xffe8)
110
111 #define IGRPMODR_SHIFT 5
112
113 /* GICD_CTLR bit definitions */
114 #define CTLR_ENABLE_G1NS_SHIFT 1
115 #define CTLR_ENABLE_G1S_SHIFT 2
116 #define CTLR_ARE_S_SHIFT 4
117 #define CTLR_ARE_NS_SHIFT 5
118 #define CTLR_DS_SHIFT 6
119 #define CTLR_E1NWF_SHIFT 7
120 #define GICD_CTLR_RWP_SHIFT 31
121
122 #define CTLR_ENABLE_G1NS_MASK U(0x1)
123 #define CTLR_ENABLE_G1S_MASK U(0x1)
124 #define CTLR_ARE_S_MASK U(0x1)
125 #define CTLR_ARE_NS_MASK U(0x1)
126 #define CTLR_DS_MASK U(0x1)
127 #define CTLR_E1NWF_MASK U(0x1)
128 #define GICD_CTLR_RWP_MASK U(0x1)
129
130 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
131 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
132 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
133 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
134 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
135 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
136 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
137
138 /* GICD_IROUTER shifts and masks */
139 #define IROUTER_SHIFT 0
140 #define IROUTER_IRM_SHIFT 31
141 #define IROUTER_IRM_MASK U(0x1)
142
143 #define GICV3_IRM_PE U(0)
144 #define GICV3_IRM_ANY U(1)
145
146 #define NUM_OF_DIST_REGS 30
147
148 /* GICD_TYPER shifts and masks */
149 #define TYPER_ESPI U(1 << 8)
150 #define TYPER_DVIS U(1 << 18)
151 #define TYPER_ESPI_RANGE_MASK U(0x1f)
152 #define TYPER_ESPI_RANGE_SHIFT U(27)
153 #define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
154
155 /*******************************************************************************
156 * Common GIC Redistributor interface registers & constants
157 ******************************************************************************/
158 #define GICR_V4_PCPUBASE_SHIFT 0x12
159 #define GICR_V3_PCPUBASE_SHIFT 0x11
160 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
161 #define GICR_CTLR U(0x0)
162 #define GICR_IIDR U(0x04)
163 #define GICR_TYPER U(0x08)
164 #define GICR_STATUSR U(0x10)
165 #define GICR_WAKER U(0x14)
166 #define GICR_PROPBASER U(0x70)
167 #define GICR_PENDBASER U(0x78)
168 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80))
169 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100))
170 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180))
171 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200))
172 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280))
173 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300))
174 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380))
175 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400))
176 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00))
177 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04))
178 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00))
179 #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00))
180
181 #define GICR_IGROUPR GICR_IGROUPR0
182 #define GICR_ISENABLER GICR_ISENABLER0
183 #define GICR_ICENABLER GICR_ICENABLER0
184 #define GICR_ISPENDR GICR_ISPENDR0
185 #define GICR_ICPENDR GICR_ICPENDR0
186 #define GICR_ISACTIVER GICR_ISACTIVER0
187 #define GICR_ICACTIVER GICR_ICACTIVER0
188 #define GICR_ICFGR GICR_ICFGR0
189 #define GICR_IGRPMODR GICR_IGRPMODR0
190
191 /* GICR_CTLR bit definitions */
192 #define GICR_CTLR_UWP_SHIFT 31
193 #define GICR_CTLR_UWP_MASK U(0x1)
194 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
195 #define GICR_CTLR_RWP_SHIFT 3
196 #define GICR_CTLR_RWP_MASK U(0x1)
197 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
198 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
199
200 /* GICR_WAKER bit definitions */
201 #define WAKER_CA_SHIFT 2
202 #define WAKER_PS_SHIFT 1
203
204 #define WAKER_CA_MASK U(0x1)
205 #define WAKER_PS_MASK U(0x1)
206
207 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
208 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
209
210 /* GICR_TYPER bit definitions */
211 #define TYPER_AFF_VAL_SHIFT 32
212 #define TYPER_PROC_NUM_SHIFT 8
213 #define TYPER_LAST_SHIFT 4
214 #define TYPER_VLPI_SHIFT 1
215
216 #define TYPER_AFF_VAL_MASK U(0xffffffff)
217 #define TYPER_PROC_NUM_MASK U(0xffff)
218 #define TYPER_LAST_MASK U(0x1)
219
220 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
221 #define TYPER_VLPI_BIT BIT_32(TYPER_VLPI_SHIFT)
222
223 #define TYPER_PPI_NUM_SHIFT U(27)
224 #define TYPER_PPI_NUM_MASK U(0x1f)
225
226 /* GICR_IIDR bit definitions */
227 #define IIDR_PRODUCT_ID_MASK U(0xff000000)
228 #define IIDR_VARIANT_MASK U(0x000f0000)
229 #define IIDR_REVISION_MASK U(0x0000f000)
230 #define IIDR_IMPLEMENTER_MASK U(0x00000fff)
231 #define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \
232 IIDR_IMPLEMENTER_MASK)
233
234 /*******************************************************************************
235 * GICv3 and 3.1 CPU interface registers & constants
236 ******************************************************************************/
237 /* ICC_SRE bit definitions */
238 #define ICC_SRE_EN_BIT BIT_32(3)
239 #define ICC_SRE_DIB_BIT BIT_32(2)
240 #define ICC_SRE_DFB_BIT BIT_32(1)
241 #define ICC_SRE_SRE_BIT BIT_32(0)
242
243 /* ICC_IGRPEN1_EL3 bit definitions */
244 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
245 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
246
247 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
248 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
249
250 /* ICC_IGRPEN0_EL1 bit definitions */
251 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
252 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
253
254 /* ICC_HPPIR0_EL1 bit definitions */
255 #define HPPIR0_EL1_INTID_SHIFT 0
256 #define HPPIR0_EL1_INTID_MASK U(0xffffff)
257
258 /* ICC_HPPIR1_EL1 bit definitions */
259 #define HPPIR1_EL1_INTID_SHIFT 0
260 #define HPPIR1_EL1_INTID_MASK U(0xffffff)
261
262 /* ICC_IAR0_EL1 bit definitions */
263 #define IAR0_EL1_INTID_SHIFT 0
264 #define IAR0_EL1_INTID_MASK U(0xffffff)
265
266 /* ICC_IAR1_EL1 bit definitions */
267 #define IAR1_EL1_INTID_SHIFT 0
268 #define IAR1_EL1_INTID_MASK U(0xffffff)
269
270 /* ICC SGI macros */
271 #define SGIR_TGT_MASK ULL(0xffff)
272 #define SGIR_AFF1_SHIFT 16
273 #define SGIR_INTID_SHIFT 24
274 #define SGIR_INTID_MASK ULL(0xf)
275 #define SGIR_AFF2_SHIFT 32
276 #define SGIR_IRM_SHIFT 40
277 #define SGIR_IRM_MASK ULL(0x1)
278 #define SGIR_AFF3_SHIFT 48
279 #define SGIR_AFF_MASK ULL(0xf)
280
281 #define SGIR_IRM_TO_AFF U(0)
282
283 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
284 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
285 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
286 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
287 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
288 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
289 ((_tgt) & SGIR_TGT_MASK))
290
291 /*****************************************************************************
292 * GICv3 and 3.1 ITS registers and constants
293 *****************************************************************************/
294 #define GITS_CTLR U(0x0)
295 #define GITS_IIDR U(0x4)
296 #define GITS_TYPER U(0x8)
297 #define GITS_CBASER U(0x80)
298 #define GITS_CWRITER U(0x88)
299 #define GITS_CREADR U(0x90)
300 #define GITS_BASER U(0x100)
301
302 /* GITS_CTLR bit definitions */
303 #define GITS_CTLR_ENABLED_BIT BIT_32(0)
304 #define GITS_CTLR_QUIESCENT_BIT BIT_32(1)
305
306 #define GITS_TYPER_VSGI BIT_64(39)
307
308 #ifndef __ASSEMBLER__
309
310 #include <stdbool.h>
311 #include <stdint.h>
312
313 #include <arch_helpers.h>
314 #include <common/interrupt_props.h>
315 #include <drivers/arm/gic_common.h>
316 #include <lib/utils_def.h>
317
gicv3_redist_size(uint64_t typer_val)318 static inline uintptr_t gicv3_redist_size(uint64_t typer_val)
319 {
320 #if GIC_ENABLE_V4_EXTN
321 if ((typer_val & TYPER_VLPI_BIT) != 0U) {
322 return 1U << GICR_V4_PCPUBASE_SHIFT;
323 } else {
324 return 1U << GICR_V3_PCPUBASE_SHIFT;
325 }
326 #else
327 return 1U << GICR_V3_PCPUBASE_SHIFT;
328 #endif
329 }
330
331 unsigned int gicv3_get_component_partnum(const uintptr_t gic_frame);
332
gicv3_is_intr_id_special_identifier(unsigned int id)333 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
334 {
335 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
336 }
337
338 /*******************************************************************************
339 * Helper GICv3 and 3.1 macros for SEL1
340 ******************************************************************************/
gicv3_acknowledge_interrupt_sel1(void)341 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
342 {
343 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
344 }
345
gicv3_get_pending_interrupt_id_sel1(void)346 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
347 {
348 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
349 }
350
gicv3_end_of_interrupt_sel1(unsigned int id)351 static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
352 {
353 /*
354 * Interrupt request deassertion from peripheral to GIC happens
355 * by clearing interrupt condition by a write to the peripheral
356 * register. It is desired that the write transfer is complete
357 * before the core tries to change GIC state from 'AP/Active' to
358 * a new state on seeing 'EOI write'.
359 * Since ICC interface writes are not ordered against Device
360 * memory writes, a barrier is required to ensure the ordering.
361 * The dsb will also ensure *completion* of previous writes with
362 * DEVICE nGnRnE attribute.
363 */
364 dsbishst();
365 write_icc_eoir1_el1(id);
366 }
367
368 /*******************************************************************************
369 * Helper GICv3 macros for EL3
370 ******************************************************************************/
gicv3_acknowledge_interrupt(void)371 static inline uint32_t gicv3_acknowledge_interrupt(void)
372 {
373 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
374 }
375
gicv3_end_of_interrupt(unsigned int id)376 static inline void gicv3_end_of_interrupt(unsigned int id)
377 {
378 /*
379 * Interrupt request deassertion from peripheral to GIC happens
380 * by clearing interrupt condition by a write to the peripheral
381 * register. It is desired that the write transfer is complete
382 * before the core tries to change GIC state from 'AP/Active' to
383 * a new state on seeing 'EOI write'.
384 * Since ICC interface writes are not ordered against Device
385 * memory writes, a barrier is required to ensure the ordering.
386 * The dsb will also ensure *completion* of previous writes with
387 * DEVICE nGnRnE attribute.
388 */
389 dsbishst();
390 return write_icc_eoir0_el1(id);
391 }
392
393 /*
394 * This macro returns the total number of GICD/GICR registers corresponding to
395 * the register name
396 */
397 #define GICD_NUM_REGS(reg_name) \
398 DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT))
399
400 #define GICR_NUM_REGS(reg_name) \
401 DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT))
402
403 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
404 #define INT_ID_MASK U(0xffffff)
405
406 /*******************************************************************************
407 * This structure describes some of the implementation defined attributes of the
408 * GICv3 IP. It is used by the platform port to specify these attributes in order
409 * to initialise the GICV3 driver. The attributes are described below.
410 *
411 * The 'gicd_base' field contains the base address of the Distributor interface
412 * programmer's view.
413 *
414 * The 'gicr_base' field contains the base address of the Re-distributor
415 * interface programmer's view.
416 *
417 * The 'interrupt_props' field is a pointer to an array that enumerates secure
418 * interrupts and their properties. If this field is not NULL, both
419 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
420 *
421 * The 'interrupt_props_num' field contains the number of entries in the
422 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
423 * and 'g1s_interrupt_num' are ignored.
424 *
425 * The 'rdistif_num' field contains the number of Redistributor interfaces the
426 * GIC implements. This is equal to the number of CPUs or CPU interfaces
427 * instantiated in the GIC.
428 *
429 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
430 * storing the base address of the Redistributor interface frame of each CPU in
431 * the system. The size of the array = 'rdistif_num'. The base addresses are
432 * detected during driver initialisation.
433 *
434 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the
435 * driver will use to convert an MPIDR value to a linear core index. This index
436 * will be used for accessing the 'rdistif_base_addrs' array. This is an
437 * optional field. A GICv3 implementation maps each MPIDR to a linear core index
438 * as well. This mapping can be found by reading the "Affinity Value" and
439 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
440 * "Processor Numbers" are suitable to index into an array to access core
441 * specific information. If this not the case, the platform port must provide a
442 * hash function. Otherwise, the "Processor Number" field will be used to access
443 * the array elements.
444 ******************************************************************************/
445 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
446
447 typedef struct gicv3_driver_data {
448 uintptr_t gicd_base;
449 uintptr_t gicr_base;
450 const interrupt_prop_t *interrupt_props;
451 unsigned int interrupt_props_num;
452 unsigned int rdistif_num;
453 uintptr_t *rdistif_base_addrs;
454 mpidr_hash_fn mpidr_to_core_pos;
455 } gicv3_driver_data_t;
456
457 typedef struct gicv3_redist_ctx {
458 /* 64 bits registers */
459 uint64_t gicr_propbaser;
460 uint64_t gicr_pendbaser;
461
462 /* 32 bits registers */
463 uint32_t gicr_ctlr;
464 uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)];
465 uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)];
466 uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)];
467 uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)];
468 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
469 uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)];
470 uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)];
471 uint32_t gicr_nsacr;
472 } gicv3_redist_ctx_t;
473
474 typedef struct gicv3_dist_ctx {
475 /* 64 bits registers */
476 uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM];
477
478 /* 32 bits registers */
479 uint32_t gicd_ctlr;
480 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
481 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
482 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
483 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
484 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
485 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
486 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
487 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
488 } gicv3_dist_ctx_t;
489
490 typedef struct gicv3_its_ctx {
491 /* 64 bits registers */
492 uint64_t gits_cbaser;
493 uint64_t gits_cwriter;
494 uint64_t gits_baser[8];
495
496 /* 32 bits registers */
497 uint32_t gits_ctlr;
498 } gicv3_its_ctx_t;
499
500 /*******************************************************************************
501 * GICv3 EL3 driver API
502 ******************************************************************************/
503 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
504 int gicv3_rdistif_probe(const uintptr_t gicr_frame);
505 void gicv3_distif_init(void);
506 void gicv3_rdistif_init(unsigned int proc_num);
507 void gicv3_rdistif_on(unsigned int proc_num);
508 void gicv3_rdistif_off(unsigned int proc_num);
509 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame);
510 void gicv3_cpuif_enable(unsigned int proc_num);
511 void gicv3_cpuif_disable(unsigned int proc_num);
512 unsigned int gicv3_get_pending_interrupt_type(void);
513 unsigned int gicv3_get_pending_interrupt_id(void);
514 unsigned int gicv3_get_interrupt_type(unsigned int id,
515 unsigned int proc_num);
516 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
517 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
518 /*
519 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
520 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
521 * implementation-defined sequence is needed at these steps, an empty function
522 * can be provided.
523 */
524 void gicv3_distif_post_restore(unsigned int proc_num);
525 void gicv3_distif_pre_save(unsigned int proc_num);
526 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
527 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
528 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
529 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
530
531 unsigned int gicv3_get_running_priority(void);
532 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
533 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
534 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
535 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
536 unsigned int priority);
537 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
538 unsigned int type);
539 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target);
540 void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
541 u_register_t mpidr);
542 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
543 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
544 unsigned int gicv3_set_pmr(unsigned int mask);
545
546 #endif /* __ASSEMBLER__ */
547 #endif /* GICV3_H */
548