1 /*
2  * Copyright 2018-2020 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef NXP_SMMU_H
9 #define NXP_SMMU_H
10 
11 #define SMMU_SCR0		(0x0)
12 #define SMMU_NSCR0		(0x400)
13 
14 #define SCR0_CLIENTPD_MASK	0x00000001
15 #define SCR0_USFCFG_MASK	0x00000400
16 
bypass_smmu(uintptr_t smmu_base_addr)17 static inline void bypass_smmu(uintptr_t smmu_base_addr)
18 {
19 	uint32_t val;
20 
21 	val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
22 		~(SCR0_USFCFG_MASK);
23 	mmio_write_32((smmu_base_addr + SMMU_SCR0), val);
24 
25 	val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
26 		~(SCR0_USFCFG_MASK);
27 	mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
28 }
29 
30 #endif
31