1 /* 2 * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DRIVERS_RAW_NAND_H 8 #define DRIVERS_RAW_NAND_H 9 10 #include <cdefs.h> 11 #include <stdint.h> 12 13 #include <drivers/nand.h> 14 15 /* NAND ONFI default value mode 0 in picosecond */ 16 #define NAND_TADL_MIN 400000UL 17 #define NAND_TALH_MIN 20000UL 18 #define NAND_TALS_MIN 50000UL 19 #define NAND_TAR_MIN 25000UL 20 #define NAND_TCCS_MIN 500000UL 21 #define NAND_TCEA_MIN 100000UL 22 #define NAND_TCEH_MIN 20000UL 23 #define NAND_TCH_MIN 20000UL 24 #define NAND_TCHZ_MAX 100000UL 25 #define NAND_TCLH_MIN 20000UL 26 #define NAND_TCLR_MIN 20000UL 27 #define NAND_TCLS_MIN 50000UL 28 #define NAND_TCOH_MIN 0UL 29 #define NAND_TCS_MIN 70000UL 30 #define NAND_TDH_MIN 20000UL 31 #define NAND_TDS_MIN 40000UL 32 #define NAND_TFEAT_MAX 1000000UL 33 #define NAND_TIR_MIN 10000UL 34 #define NAND_TITC_MIN 1000000UL 35 #define NAND_TR_MAX 200000000UL 36 #define NAND_TRC_MIN 100000UL 37 #define NAND_TREA_MAX 40000UL 38 #define NAND_TREH_MIN 30000UL 39 #define NAND_TRHOH_MIN 0UL 40 #define NAND_TRHW_MIN 200000UL 41 #define NAND_TRHZ_MAX 200000UL 42 #define NAND_TRLOH_MIN 0UL 43 #define NAND_TRP_MIN 50000UL 44 #define NAND_TRR_MIN 40000UL 45 #define NAND_TRST_MAX 250000000000ULL 46 #define NAND_TWB_MAX 200000UL 47 #define NAND_TWC_MIN 100000UL 48 #define NAND_TWH_MIN 30000UL 49 #define NAND_TWHR_MIN 120000UL 50 #define NAND_TWP_MIN 50000UL 51 #define NAND_TWW_MIN 100000UL 52 53 /* NAND request types */ 54 #define NAND_REQ_CMD 0x0000U 55 #define NAND_REQ_ADDR 0x1000U 56 #define NAND_REQ_DATAIN 0x2000U 57 #define NAND_REQ_DATAOUT 0x3000U 58 #define NAND_REQ_WAIT 0x4000U 59 #define NAND_REQ_MASK GENMASK(14, 12) 60 #define NAND_REQ_BUS_WIDTH_8 BIT(15) 61 62 #define PARAM_PAGE_SIZE 256 63 64 /* NAND ONFI commands */ 65 #define NAND_CMD_READ_1ST 0x00U 66 #define NAND_CMD_CHANGE_1ST 0x05U 67 #define NAND_CMD_READID_SIG_ADDR 0x20U 68 #define NAND_CMD_READ_2ND 0x30U 69 #define NAND_CMD_STATUS 0x70U 70 #define NAND_CMD_READID 0x90U 71 #define NAND_CMD_CHANGE_2ND 0xE0U 72 #define NAND_CMD_READ_PARAM_PAGE 0xECU 73 #define NAND_CMD_RESET 0xFFU 74 75 #define ONFI_REV_21 BIT(3) 76 #define ONFI_FEAT_BUS_WIDTH_16 BIT(0) 77 #define ONFI_FEAT_EXTENDED_PARAM BIT(7) 78 79 /* NAND ECC type */ 80 #define NAND_ECC_NONE U(0) 81 #define NAND_ECC_HW U(1) 82 #define NAND_ECC_ONDIE U(2) 83 84 /* NAND bus width */ 85 #define NAND_BUS_WIDTH_8 U(0) 86 #define NAND_BUS_WIDTH_16 U(1) 87 88 struct nand_req { 89 struct nand_device *nand; 90 uint16_t type; 91 uint8_t *addr; 92 unsigned int length; 93 unsigned int delay_ms; 94 unsigned int inst_delay; 95 }; 96 97 struct nand_param_page { 98 /* Rev information and feature block */ 99 uint32_t page_sig; 100 uint16_t rev; 101 uint16_t features; 102 uint16_t opt_cmd; 103 uint8_t jtg; 104 uint8_t train_cmd; 105 uint16_t ext_param_length; 106 uint8_t nb_param_pages; 107 uint8_t reserved1[17]; 108 /* Manufacturer information */ 109 uint8_t manufacturer[12]; 110 uint8_t model[20]; 111 uint8_t manufacturer_id; 112 uint16_t data_code; 113 uint8_t reserved2[13]; 114 /* Memory organization */ 115 uint32_t bytes_per_page; 116 uint16_t spare_per_page; 117 uint32_t bytes_per_partial; 118 uint16_t spare_per_partial; 119 uint32_t num_pages_per_blk; 120 uint32_t num_blk_in_lun; 121 uint8_t num_lun; 122 uint8_t num_addr_cycles; 123 uint8_t bit_per_cell; 124 uint16_t max_bb_per_lun; 125 uint16_t blk_endur; 126 uint8_t valid_blk_begin; 127 uint16_t blk_enbur_valid; 128 uint8_t nb_prog_page; 129 uint8_t partial_prog_attr; 130 uint8_t nb_ecc_bits; 131 uint8_t plane_addr; 132 uint8_t mplanes_ops; 133 uint8_t ez_nand; 134 uint8_t reserved3[12]; 135 /* Electrical parameters */ 136 uint8_t io_pin_cap_max; 137 uint16_t sdr_timing_mode; 138 uint16_t sdr_prog_cache_timing; 139 uint16_t tprog; 140 uint16_t tbers; 141 uint16_t tr; 142 uint16_t tccs; 143 uint8_t nvddr_timing_mode; 144 uint8_t nvddr2_timing_mode; 145 uint8_t nvddr_features; 146 uint16_t clk_input_cap_typ; 147 uint16_t io_pin_cap_typ; 148 uint16_t input_pin_cap_typ; 149 uint8_t input_pin_cap_max; 150 uint8_t drv_strength_support; 151 uint16_t tr_max; 152 uint16_t tadl; 153 uint16_t tr_typ; 154 uint8_t reserved4[6]; 155 /* Vendor block */ 156 uint16_t vendor_revision; 157 uint8_t vendor[88]; 158 uint16_t crc16; 159 } __packed; 160 161 struct nand_ctrl_ops { 162 int (*exec)(struct nand_req *req); 163 void (*setup)(struct nand_device *nand); 164 }; 165 166 struct rawnand_device { 167 struct nand_device *nand_dev; 168 const struct nand_ctrl_ops *ops; 169 }; 170 171 int nand_raw_init(unsigned long long *size, unsigned int *erase_size); 172 int nand_wait_ready(unsigned int delay_ms); 173 int nand_read_page_cmd(unsigned int page, unsigned int offset, 174 uintptr_t buffer, unsigned int len); 175 int nand_change_read_column_cmd(unsigned int offset, uintptr_t buffer, 176 unsigned int len); 177 void nand_raw_ctrl_init(const struct nand_ctrl_ops *ops); 178 179 /* 180 * Platform can implement this to override default raw NAND instance 181 * configuration. 182 * 183 * @device: target raw NAND instance. 184 * Return 0 on success, negative value otherwise. 185 */ 186 int plat_get_raw_nand_data(struct rawnand_device *device); 187 188 #endif /* DRIVERS_RAW_NAND_H */ 189