1 /* 2 * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DDR_REGS_H 8 #define STM32MP1_DDR_REGS_H 9 10 #include <lib/utils_def.h> 11 12 /* DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL) registers */ 13 struct stm32mp1_ddrctl { 14 uint32_t mstr ; /* 0x0 Master */ 15 uint32_t stat; /* 0x4 Operating Mode Status */ 16 uint8_t reserved008[0x10 - 0x8]; 17 uint32_t mrctrl0; /* 0x10 Control 0 */ 18 uint32_t mrctrl1; /* 0x14 Control 1 */ 19 uint32_t mrstat; /* 0x18 Status */ 20 uint32_t reserved01c; /* 0x1c */ 21 uint32_t derateen; /* 0x20 Temperature Derate Enable */ 22 uint32_t derateint; /* 0x24 Temperature Derate Interval */ 23 uint8_t reserved028[0x30 - 0x28]; 24 uint32_t pwrctl; /* 0x30 Low Power Control */ 25 uint32_t pwrtmg; /* 0x34 Low Power Timing */ 26 uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */ 27 uint8_t reserved03c[0x50 - 0x3C]; 28 uint32_t rfshctl0; /* 0x50 Refresh Control 0 */ 29 uint32_t reserved054; /* 0x54 Refresh Control 1 */ 30 uint32_t reserved058; /* 0x58 Refresh Control 2 */ 31 uint32_t reserved05C; 32 uint32_t rfshctl3; /* 0x60 Refresh Control 0 */ 33 uint32_t rfshtmg; /* 0x64 Refresh Timing */ 34 uint8_t reserved068[0xc0 - 0x68]; 35 uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */ 36 uint32_t reserved0c4; /* 0xc4 CRC Parity Control1 */ 37 uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */ 38 uint32_t crcparstat; /* 0xcc CRC Parity Status */ 39 uint32_t init0; /* 0xd0 SDRAM Initialization 0 */ 40 uint32_t init1; /* 0xd4 SDRAM Initialization 1 */ 41 uint32_t init2; /* 0xd8 SDRAM Initialization 2 */ 42 uint32_t init3; /* 0xdc SDRAM Initialization 3 */ 43 uint32_t init4; /* 0xe0 SDRAM Initialization 4 */ 44 uint32_t init5; /* 0xe4 SDRAM Initialization 5 */ 45 uint32_t reserved0e8; 46 uint32_t reserved0ec; 47 uint32_t dimmctl; /* 0xf0 DIMM Control */ 48 uint8_t reserved0f4[0x100 - 0xf4]; 49 uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */ 50 uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */ 51 uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */ 52 uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */ 53 uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */ 54 uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */ 55 uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */ 56 uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */ 57 uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */ 58 uint8_t reserved124[0x138 - 0x124]; 59 uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */ 60 uint32_t dramtmg15; /* 0x13C SDRAM Timing 15 */ 61 uint8_t reserved140[0x180 - 0x140]; 62 uint32_t zqctl0; /* 0x180 ZQ Control 0 */ 63 uint32_t zqctl1; /* 0x184 ZQ Control 1 */ 64 uint32_t zqctl2; /* 0x188 ZQ Control 2 */ 65 uint32_t zqstat; /* 0x18c ZQ Status */ 66 uint32_t dfitmg0; /* 0x190 DFI Timing 0 */ 67 uint32_t dfitmg1; /* 0x194 DFI Timing 1 */ 68 uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */ 69 uint32_t reserved19c; 70 uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */ 71 uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */ 72 uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */ 73 uint32_t reserved1ac; 74 uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */ 75 uint8_t reserved1b4[0x1bc - 0x1b4]; 76 uint32_t dfistat; /* 0x1bc DFI Miscellaneous Control */ 77 uint8_t reserved1c0[0x1c4 - 0x1c0]; 78 uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */ 79 uint8_t reserved1c8[0x204 - 0x1c8]; 80 uint32_t addrmap1; /* 0x204 Address Map 1 */ 81 uint32_t addrmap2; /* 0x208 Address Map 2 */ 82 uint32_t addrmap3; /* 0x20c Address Map 3 */ 83 uint32_t addrmap4; /* 0x210 Address Map 4 */ 84 uint32_t addrmap5; /* 0x214 Address Map 5 */ 85 uint32_t addrmap6; /* 0x218 Address Map 6 */ 86 uint8_t reserved21c[0x224 - 0x21c]; 87 uint32_t addrmap9; /* 0x224 Address Map 9 */ 88 uint32_t addrmap10; /* 0x228 Address Map 10 */ 89 uint32_t addrmap11; /* 0x22C Address Map 11 */ 90 uint8_t reserved230[0x240 - 0x230]; 91 uint32_t odtcfg; /* 0x240 ODT Configuration */ 92 uint32_t odtmap; /* 0x244 ODT/Rank Map */ 93 uint8_t reserved248[0x250 - 0x248]; 94 uint32_t sched; /* 0x250 Scheduler Control */ 95 uint32_t sched1; /* 0x254 Scheduler Control 1 */ 96 uint32_t reserved258; 97 uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */ 98 uint32_t reserved260; 99 uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */ 100 uint32_t reserved268; 101 uint32_t perfwr1; /* 0x26c Write CAM 1 */ 102 uint8_t reserved27c[0x300 - 0x270]; 103 uint32_t dbg0; /* 0x300 Debug 0 */ 104 uint32_t dbg1; /* 0x304 Debug 1 */ 105 uint32_t dbgcam; /* 0x308 CAM Debug */ 106 uint32_t dbgcmd; /* 0x30c Command Debug */ 107 uint32_t dbgstat; /* 0x310 Status Debug */ 108 uint8_t reserved314[0x320 - 0x314]; 109 uint32_t swctl; /* 0x320 Software Programming Control Enable */ 110 uint32_t swstat; /* 0x324 Software Programming Control Status */ 111 uint8_t reserved328[0x36c - 0x328]; 112 uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */ 113 uint32_t poisonstat; /* 0x370 AXI Poison Status Register */ 114 uint8_t reserved374[0x3fc - 0x374]; 115 116 /* Multi Port registers */ 117 uint32_t pstat; /* 0x3fc Port Status */ 118 uint32_t pccfg; /* 0x400 Port Common Configuration */ 119 120 /* PORT 0 */ 121 uint32_t pcfgr_0; /* 0x404 Configuration Read */ 122 uint32_t pcfgw_0; /* 0x408 Configuration Write */ 123 uint8_t reserved40c[0x490 - 0x40c]; 124 uint32_t pctrl_0; /* 0x490 Port Control Register */ 125 uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */ 126 uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */ 127 uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */ 128 uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */ 129 uint8_t reserved4a4[0x4b4 - 0x4a4]; 130 131 /* PORT 1 */ 132 uint32_t pcfgr_1; /* 0x4b4 Configuration Read */ 133 uint32_t pcfgw_1; /* 0x4b8 Configuration Write */ 134 uint8_t reserved4bc[0x540 - 0x4bc]; 135 uint32_t pctrl_1; /* 0x540 Port 2 Control Register */ 136 uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */ 137 uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */ 138 uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */ 139 uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */ 140 } __packed; 141 142 /* DDR Physical Interface Control (DDRPHYC) registers*/ 143 struct stm32mp1_ddrphy { 144 uint32_t ridr; /* 0x00 R Revision Identification */ 145 uint32_t pir; /* 0x04 R/W PHY Initialization */ 146 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */ 147 uint32_t pgsr; /* 0x0C PHY General Status */ 148 uint32_t dllgcr; /* 0x10 R/W DLL General Control */ 149 uint32_t acdllcr; /* 0x14 R/W AC DLL Control */ 150 uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */ 151 uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */ 152 uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */ 153 uint32_t aciocr; /* 0x24 AC I/O Configuration */ 154 uint32_t dxccr; /* 0x28 DATX8 Common Configuration */ 155 uint32_t dsgcr; /* 0x2C DDR System General Configuration */ 156 uint32_t dcr; /* 0x30 DRAM Configuration */ 157 uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */ 158 uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */ 159 uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */ 160 uint32_t mr0; /* 0x40 Mode 0 */ 161 uint32_t mr1; /* 0x44 Mode 1 */ 162 uint32_t mr2; /* 0x48 Mode 2 */ 163 uint32_t mr3; /* 0x4C Mode 3 */ 164 uint32_t odtcr; /* 0x50 ODT Configuration */ 165 uint32_t dtar; /* 0x54 data training address */ 166 uint32_t dtdr0; /* 0x58 */ 167 uint32_t dtdr1; /* 0x5c */ 168 uint8_t res1[0x0c0 - 0x060]; /* 0x60 */ 169 uint32_t dcuar; /* 0xc0 Address */ 170 uint32_t dcudr; /* 0xc4 DCU Data */ 171 uint32_t dcurr; /* 0xc8 DCU Run */ 172 uint32_t dculr; /* 0xcc DCU Loop */ 173 uint32_t dcugcr; /* 0xd0 DCU General Configuration */ 174 uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */ 175 uint32_t dcusr0; /* 0xd8 DCU Status 0 */ 176 uint32_t dcusr1; /* 0xdc DCU Status 1 */ 177 uint8_t res2[0x100 - 0xe0]; /* 0xe0 */ 178 uint32_t bistrr; /* 0x100 BIST Run */ 179 uint32_t bistmskr0; /* 0x104 BIST Mask 0 */ 180 uint32_t bistmskr1; /* 0x108 BIST Mask 0 */ 181 uint32_t bistwcr; /* 0x10c BIST Word Count */ 182 uint32_t bistlsr; /* 0x110 BIST LFSR Seed */ 183 uint32_t bistar0; /* 0x114 BIST Address 0 */ 184 uint32_t bistar1; /* 0x118 BIST Address 1 */ 185 uint32_t bistar2; /* 0x11c BIST Address 2 */ 186 uint32_t bistupdr; /* 0x120 BIST User Data Pattern */ 187 uint32_t bistgsr; /* 0x124 BIST General Status */ 188 uint32_t bistwer; /* 0x128 BIST Word Error */ 189 uint32_t bistber0; /* 0x12c BIST Bit Error 0 */ 190 uint32_t bistber1; /* 0x130 BIST Bit Error 1 */ 191 uint32_t bistber2; /* 0x134 BIST Bit Error 2 */ 192 uint32_t bistwcsr; /* 0x138 BIST Word Count Status */ 193 uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */ 194 uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */ 195 uint8_t res3[0x178 - 0x144]; /* 0x144 */ 196 uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */ 197 uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */ 198 uint32_t zq0cr0; /* 0x180 zq 0 control 0 */ 199 uint32_t zq0cr1; /* 0x184 zq 0 control 1 */ 200 uint32_t zq0sr0; /* 0x188 zq 0 status 0 */ 201 uint32_t zq0sr1; /* 0x18C zq 0 status 1 */ 202 uint8_t res4[0x1C0 - 0x190]; /* 0x190 */ 203 uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */ 204 uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */ 205 uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */ 206 uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */ 207 uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */ 208 uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */ 209 uint8_t res5[0x200 - 0x1d8]; /* 0x1d8 */ 210 uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */ 211 uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */ 212 uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */ 213 uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */ 214 uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */ 215 uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */ 216 uint8_t res6[0x240 - 0x218]; /* 0x218 */ 217 uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */ 218 uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */ 219 uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */ 220 uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */ 221 uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */ 222 uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */ 223 uint8_t res7[0x280 - 0x258]; /* 0x258 */ 224 uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */ 225 uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */ 226 uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */ 227 uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */ 228 uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */ 229 uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */ 230 } __packed; 231 232 /* DDR Controller registers offsets */ 233 #define DDRCTRL_MSTR 0x000 234 #define DDRCTRL_STAT 0x004 235 #define DDRCTRL_MRCTRL0 0x010 236 #define DDRCTRL_MRSTAT 0x018 237 #define DDRCTRL_PWRCTL 0x030 238 #define DDRCTRL_PWRTMG 0x034 239 #define DDRCTRL_HWLPCTL 0x038 240 #define DDRCTRL_RFSHCTL3 0x060 241 #define DDRCTRL_RFSHTMG 0x064 242 #define DDRCTRL_INIT0 0x0D0 243 #define DDRCTRL_DFIMISC 0x1B0 244 #define DDRCTRL_DBG1 0x304 245 #define DDRCTRL_DBGCAM 0x308 246 #define DDRCTRL_DBGCMD 0x30C 247 #define DDRCTRL_DBGSTAT 0x310 248 #define DDRCTRL_SWCTL 0x320 249 #define DDRCTRL_SWSTAT 0x324 250 #define DDRCTRL_PSTAT 0x3FC 251 #define DDRCTRL_PCTRL_0 0x490 252 #define DDRCTRL_PCTRL_1 0x540 253 254 /* DDR Controller Register fields */ 255 #define DDRCTRL_MSTR_DDR3 BIT(0) 256 #define DDRCTRL_MSTR_LPDDR2 BIT(2) 257 #define DDRCTRL_MSTR_LPDDR3 BIT(3) 258 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12) 259 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0 260 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12) 261 #define DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER BIT(13) 262 #define DDRCTRL_MSTR_DLL_OFF_MODE BIT(15) 263 264 #define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) 265 #define DDRCTRL_STAT_OPERATING_MODE_NORMAL BIT(0) 266 #define DDRCTRL_STAT_OPERATING_MODE_SR (BIT(0) | BIT(1)) 267 #define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) 268 #define DDRCTRL_STAT_SELFREF_TYPE_ASR (BIT(4) | BIT(5)) 269 #define DDRCTRL_STAT_SELFREF_TYPE_SR BIT(5) 270 271 #define DDRCTRL_MRCTRL0_MR_TYPE_WRITE U(0) 272 /* Only one rank supported */ 273 #define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4 274 #define DDRCTRL_MRCTRL0_MR_RANK_ALL \ 275 BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT) 276 #define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12 277 #define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12) 278 #define DDRCTRL_MRCTRL0_MR_WR BIT(31) 279 280 #define DDRCTRL_MRSTAT_MR_WR_BUSY BIT(0) 281 282 #define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) 283 #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) 284 #define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) 285 #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) 286 287 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) 288 #define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) 289 290 #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) 291 292 #define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) 293 294 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) 295 #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT 16 296 297 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK GENMASK(31, 30) 298 #define DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL BIT(30) 299 300 #define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) 301 302 #define DDRCTRL_DBG1_DIS_HIF BIT(1) 303 304 #define DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY BIT(29) 305 #define DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY BIT(28) 306 #define DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY BIT(26) 307 #define DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH GENMASK(12, 8) 308 #define DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH GENMASK(4, 0) 309 #define DDRCTRL_DBGCAM_DATA_PIPELINE_EMPTY \ 310 (DDRCTRL_DBGCAM_WR_DATA_PIPELINE_EMPTY | \ 311 DDRCTRL_DBGCAM_RD_DATA_PIPELINE_EMPTY) 312 #define DDRCTRL_DBGCAM_DBG_Q_DEPTH \ 313 (DDRCTRL_DBGCAM_DBG_WR_Q_EMPTY | \ 314 DDRCTRL_DBGCAM_DBG_LPR_Q_DEPTH | \ 315 DDRCTRL_DBGCAM_DBG_HPR_Q_DEPTH) 316 317 #define DDRCTRL_DBGCMD_RANK0_REFRESH BIT(0) 318 319 #define DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY BIT(0) 320 321 #define DDRCTRL_SWCTL_SW_DONE BIT(0) 322 323 #define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) 324 325 #define DDRCTRL_PCTRL_N_PORT_EN BIT(0) 326 327 /* DDR PHY registers offsets */ 328 #define DDRPHYC_PIR 0x004 329 #define DDRPHYC_PGCR 0x008 330 #define DDRPHYC_PGSR 0x00C 331 #define DDRPHYC_DLLGCR 0x010 332 #define DDRPHYC_ACDLLCR 0x014 333 #define DDRPHYC_PTR0 0x018 334 #define DDRPHYC_ACIOCR 0x024 335 #define DDRPHYC_DXCCR 0x028 336 #define DDRPHYC_DSGCR 0x02C 337 #define DDRPHYC_ZQ0CR0 0x180 338 #define DDRPHYC_DX0GCR 0x1C0 339 #define DDRPHYC_DX0DLLCR 0x1CC 340 #define DDRPHYC_DX1GCR 0x200 341 #define DDRPHYC_DX1DLLCR 0x20C 342 #define DDRPHYC_DX2GCR 0x240 343 #define DDRPHYC_DX2DLLCR 0x24C 344 #define DDRPHYC_DX3GCR 0x280 345 #define DDRPHYC_DX3DLLCR 0x28C 346 347 /* DDR PHY Register fields */ 348 #define DDRPHYC_PIR_INIT BIT(0) 349 #define DDRPHYC_PIR_DLLSRST BIT(1) 350 #define DDRPHYC_PIR_DLLLOCK BIT(2) 351 #define DDRPHYC_PIR_ZCAL BIT(3) 352 #define DDRPHYC_PIR_ITMSRST BIT(4) 353 #define DDRPHYC_PIR_DRAMRST BIT(5) 354 #define DDRPHYC_PIR_DRAMINIT BIT(6) 355 #define DDRPHYC_PIR_QSTRN BIT(7) 356 #define DDRPHYC_PIR_ICPC BIT(16) 357 #define DDRPHYC_PIR_ZCALBYP BIT(30) 358 #define DDRPHYC_PIR_INITSTEPS_MASK GENMASK(31, 7) 359 360 #define DDRPHYC_PGCR_DFTCMP BIT(2) 361 #define DDRPHYC_PGCR_PDDISDX BIT(24) 362 #define DDRPHYC_PGCR_RFSHDT_MASK GENMASK(28, 25) 363 364 #define DDRPHYC_PGSR_IDONE BIT(0) 365 #define DDRPHYC_PGSR_DTERR BIT(5) 366 #define DDRPHYC_PGSR_DTIERR BIT(6) 367 #define DDRPHYC_PGSR_DFTERR BIT(7) 368 #define DDRPHYC_PGSR_RVERR BIT(8) 369 #define DDRPHYC_PGSR_RVEIRR BIT(9) 370 371 #define DDRPHYC_DLLGCR_BPS200 BIT(23) 372 373 #define DDRPHYC_ACDLLCR_DLLSRST BIT(30) 374 #define DDRPHYC_ACDLLCR_DLLDIS BIT(31) 375 376 #define DDRPHYC_PTR0_TDLLSRST_OFFSET 0 377 #define DDRPHYC_PTR0_TDLLSRST_MASK GENMASK(5, 0) 378 #define DDRPHYC_PTR0_TDLLLOCK_OFFSET 6 379 #define DDRPHYC_PTR0_TDLLLOCK_MASK GENMASK(17, 6) 380 #define DDRPHYC_PTR0_TITMSRST_OFFSET 18 381 #define DDRPHYC_PTR0_TITMSRST_MASK GENMASK(21, 18) 382 383 #define DDRPHYC_ACIOCR_ACPDD BIT(3) 384 #define DDRPHYC_ACIOCR_ACPDR BIT(4) 385 #define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8) 386 #define DDRPHYC_ACIOCR_CKPDD_0 BIT(8) 387 #define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11) 388 #define DDRPHYC_ACIOCR_CKPDR_0 BIT(11) 389 #define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(21, 18) 390 #define DDRPHYC_ACIOCR_CSPDD_0 BIT(18) 391 #define DDRPHYC_ACIOCR_RSTPDD BIT(27) 392 #define DDRPHYC_ACIOCR_RSTPDR BIT(28) 393 394 #define DDRPHYC_DXCCR_DXPDD BIT(2) 395 #define DDRPHYC_DXCCR_DXPDR BIT(3) 396 397 #define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16) 398 #define DDRPHYC_DSGCR_CKEPDD_0 BIT(16) 399 #define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20) 400 #define DDRPHYC_DSGCR_ODTPDD_0 BIT(20) 401 #define DDRPHYC_DSGCR_NL2PD BIT(24) 402 403 #define DDRPHYC_ZQ0CRN_ZDATA_MASK GENMASK(27, 0) 404 #define DDRPHYC_ZQ0CRN_ZDATA_SHIFT 0 405 #define DDRPHYC_ZQ0CRN_ZDEN BIT(28) 406 #define DDRPHYC_ZQ0CRN_ZQPD BIT(31) 407 408 #define DDRPHYC_DXNGCR_DXEN BIT(0) 409 410 #define DDRPHYC_DXNDLLCR_DLLSRST BIT(30) 411 #define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) 412 #define DDRPHYC_DXNDLLCR_SDPHASE_MASK GENMASK(17, 14) 413 #define DDRPHYC_DXNDLLCR_SDPHASE_SHIFT 14 414 415 #endif /* STM32MP1_DDR_REGS_H */ 416