1 /* 2 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H 8 #define ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H 9 10 /* EXPORT HEADER -- See include/export/README for details! -- EXPORT HEADER */ 11 12 #include "../lib/utils_def_exp.h" 13 #include "param_header_exp.h" 14 15 /******************************************************************************* 16 * Constants that allow assembler code to access members of and the 17 * 'entry_point_info' structure at their correct offsets. 18 ******************************************************************************/ 19 #define ENTRY_POINT_INFO_PC_OFFSET U(0x08) 20 #ifdef __aarch64__ 21 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x18) 22 #else 23 #define ENTRY_POINT_INFO_LR_SVC_OFFSET U(0x10) 24 #define ENTRY_POINT_INFO_ARGS_OFFSET U(0x14) 25 #endif 26 27 /* 28 * Security state of the image. Bit 0 and 29 * bit 5 are used to determine the security 30 * state of the image as follows: 31 * 32 * --------------------------------- 33 * Bit 5 | Bit 0 | Security state 34 * --------------------------------- 35 * 0 0 EP_SECURE 36 * 0 1 EP_NON_SECURE 37 * 1 1 EP_REALM 38 */ 39 #define EP_SECURITY_MASK UL(0x21) 40 #define EP_SECURITY_SHIFT UL(0) 41 #define EP_SECURE UL(0x0) 42 #define EP_NON_SECURE UL(0x1) 43 #define EP_REALM UL(0x21) 44 45 /* Endianness of the image. */ 46 #define EP_EE_MASK U(0x2) 47 #define EP_EE_SHIFT U(1) 48 #define EP_EE_LITTLE U(0x0) 49 #define EP_EE_BIG U(0x2) 50 #define EP_GET_EE(x) ((x) & EP_EE_MASK) 51 #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) 52 53 /* Enable or disable access to the secure timer from secure images. */ 54 #define EP_ST_MASK U(0x4) 55 #define EP_ST_SHIFT U(2) 56 #define EP_ST_DISABLE U(0x0) 57 #define EP_ST_ENABLE U(0x4) 58 #define EP_GET_ST(x) ((x) & EP_ST_MASK) 59 #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) 60 61 /* Determine if an image is executable or not. */ 62 #define EP_EXE_MASK U(0x8) 63 #define EP_EXE_SHIFT U(3) 64 #define EP_NON_EXECUTABLE U(0x0) 65 #define EP_EXECUTABLE U(0x8) 66 #define EP_GET_EXE(x) ((x) & EP_EXE_MASK) 67 #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) 68 69 /* Flag to indicate the first image that is executed. */ 70 #define EP_FIRST_EXE_MASK U(0x10) 71 #define EP_FIRST_EXE_SHIFT U(4) 72 #define EP_FIRST_EXE U(0x10) 73 #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) 74 #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) 75 76 #ifndef __ASSEMBLER__ 77 78 typedef struct aapcs64_params { 79 uint64_t arg0; 80 uint64_t arg1; 81 uint64_t arg2; 82 uint64_t arg3; 83 uint64_t arg4; 84 uint64_t arg5; 85 uint64_t arg6; 86 uint64_t arg7; 87 } aapcs64_params_t; 88 89 typedef struct aapcs32_params { 90 uint32_t arg0; 91 uint32_t arg1; 92 uint32_t arg2; 93 uint32_t arg3; 94 } aapcs32_params_t; 95 96 /***************************************************************************** 97 * This structure represents the superset of information needed while 98 * switching exception levels. The only two mechanisms to do so are 99 * ERET & SMC. Security state is indicated using bit zero of header 100 * attribute 101 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start 102 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while 103 * processing SMC to jump to BL31. 104 *****************************************************************************/ 105 typedef struct entry_point_info { 106 param_header_t h; 107 uintptr_t pc; 108 uint32_t spsr; 109 #ifdef __aarch64__ 110 aapcs64_params_t args; 111 #else 112 uintptr_t lr_svc; 113 aapcs32_params_t args; 114 #endif 115 } entry_point_info_t; 116 117 #endif /*__ASSEMBLER__*/ 118 119 #endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_EP_INFO_EXP_H */ 120