1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/spinlock.h> 17 #include <lib/utils_def.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 20 /******************************************************************************* 21 * Forward declarations 22 ******************************************************************************/ 23 struct meminfo; 24 struct image_info; 25 struct bl_params; 26 27 typedef struct arm_tzc_regions_info { 28 unsigned long long base; 29 unsigned long long end; 30 unsigned int sec_attr; 31 unsigned int nsaid_permissions; 32 } arm_tzc_regions_info_t; 33 34 /******************************************************************************* 35 * Default mapping definition of the TrustZone Controller for ARM standard 36 * platforms. 37 * Configure: 38 * - Region 0 with no access; 39 * - Region 1 with secure access only; 40 * - the remaining DRAM regions access from the given Non-Secure masters. 41 ******************************************************************************/ 42 #if SPM_MM 43 #define ARM_TZC_REGIONS_DEF \ 44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 45 TZC_REGION_S_RDWR, 0}, \ 46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 50 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 52 PLAT_ARM_TZC_NS_DEV_ACCESS} 53 54 #elif ENABLE_RME 55 #define ARM_TZC_REGIONS_DEF \ 56 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 57 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 60 {ARM_REALM_BASE, ARM_REALM_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 61 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 62 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 63 PLAT_ARM_TZC_NS_DEV_ACCESS} 64 65 #else 66 #define ARM_TZC_REGIONS_DEF \ 67 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 68 TZC_REGION_S_RDWR, 0}, \ 69 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 70 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 71 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 72 PLAT_ARM_TZC_NS_DEV_ACCESS} 73 #endif 74 75 #define ARM_CASSERT_MMAP \ 76 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 77 assert_plat_arm_mmap_mismatch); \ 78 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 79 <= MAX_MMAP_REGIONS, \ 80 assert_max_mmap_regions); 81 82 void arm_setup_romlib(void); 83 84 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 85 /* 86 * Use this macro to instantiate lock before it is used in below 87 * arm_lock_xxx() macros 88 */ 89 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 90 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 91 92 #if !HW_ASSISTED_COHERENCY 93 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 94 #else 95 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 96 #endif 97 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 98 99 /* 100 * These are wrapper macros to the Coherent Memory Bakery Lock API. 101 */ 102 #define arm_lock_init() bakery_lock_init(&arm_lock) 103 #define arm_lock_get() bakery_lock_get(&arm_lock) 104 #define arm_lock_release() bakery_lock_release(&arm_lock) 105 106 #else 107 108 /* 109 * Empty macros for all other BL stages other than BL31 and BL32 110 */ 111 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 112 #define ARM_LOCK_GET_INSTANCE 0 113 #define arm_lock_init() 114 #define arm_lock_get() 115 #define arm_lock_release() 116 117 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 118 119 #if ARM_RECOM_STATE_ID_ENC 120 /* 121 * Macros used to parse state information from State-ID if it is using the 122 * recommended encoding for State-ID. 123 */ 124 #define ARM_LOCAL_PSTATE_WIDTH 4 125 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 126 127 /* Macros to construct the composite power state */ 128 129 /* Make composite power state parameter till power level 0 */ 130 #if PSCI_EXTENDED_STATE_ID 131 132 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 133 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 134 #else 135 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 136 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 137 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 138 ((type) << PSTATE_TYPE_SHIFT)) 139 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 140 141 /* Make composite power state parameter till power level 1 */ 142 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 143 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 144 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 145 146 /* Make composite power state parameter till power level 2 */ 147 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 148 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 149 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 150 151 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 152 153 /* ARM State switch error codes */ 154 #define STATE_SW_E_PARAM (-2) 155 #define STATE_SW_E_DENIED (-3) 156 157 /* plat_get_rotpk_info() flags */ 158 #define ARM_ROTPK_REGS_ID 1 159 #define ARM_ROTPK_DEVEL_RSA_ID 2 160 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 161 162 163 /* IO storage utility functions */ 164 int arm_io_setup(void); 165 166 /* Set image specification in IO block policy */ 167 int arm_set_image_source(unsigned int image_id, const char *part_name, 168 uintptr_t *dev_handle, uintptr_t *image_spec); 169 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 170 171 /* Security utility functions */ 172 void arm_tzc400_setup(uintptr_t tzc_base, 173 const arm_tzc_regions_info_t *tzc_regions); 174 struct tzc_dmc500_driver_data; 175 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 176 const arm_tzc_regions_info_t *tzc_regions); 177 178 /* Console utility functions */ 179 void arm_console_boot_init(void); 180 void arm_console_boot_end(void); 181 void arm_console_runtime_init(void); 182 void arm_console_runtime_end(void); 183 184 /* Systimer utility function */ 185 void arm_configure_sys_timer(void); 186 187 /* PM utility functions */ 188 int arm_validate_power_state(unsigned int power_state, 189 psci_power_state_t *req_state); 190 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 191 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 192 void arm_system_pwr_domain_save(void); 193 void arm_system_pwr_domain_resume(void); 194 int arm_psci_read_mem_protect(int *enabled); 195 int arm_nor_psci_write_mem_protect(int val); 196 void arm_nor_psci_do_static_mem_protect(void); 197 void arm_nor_psci_do_dyn_mem_protect(void); 198 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 199 200 /* Topology utility function */ 201 int arm_check_mpidr(u_register_t mpidr); 202 203 /* BL1 utility functions */ 204 void arm_bl1_early_platform_setup(void); 205 void arm_bl1_platform_setup(void); 206 void arm_bl1_plat_arch_setup(void); 207 208 /* BL2 utility functions */ 209 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 210 void arm_bl2_platform_setup(void); 211 void arm_bl2_plat_arch_setup(void); 212 uint32_t arm_get_spsr_for_bl32_entry(void); 213 uint32_t arm_get_spsr_for_bl33_entry(void); 214 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 215 int arm_bl2_handle_post_image_load(unsigned int image_id); 216 struct bl_params *arm_get_next_bl_params(void); 217 218 /* BL2 at EL3 functions */ 219 void arm_bl2_el3_early_platform_setup(void); 220 void arm_bl2_el3_plat_arch_setup(void); 221 222 /* BL2U utility functions */ 223 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 224 void *plat_info); 225 void arm_bl2u_platform_setup(void); 226 void arm_bl2u_plat_arch_setup(void); 227 228 /* BL31 utility functions */ 229 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 230 uintptr_t hw_config, void *plat_params_from_bl2); 231 void arm_bl31_platform_setup(void); 232 void arm_bl31_plat_runtime_setup(void); 233 void arm_bl31_plat_arch_setup(void); 234 235 /* TSP utility functions */ 236 void arm_tsp_early_platform_setup(void); 237 238 /* SP_MIN utility functions */ 239 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 240 uintptr_t hw_config, void *plat_params_from_bl2); 241 void arm_sp_min_plat_runtime_setup(void); 242 void arm_sp_min_plat_arch_setup(void); 243 244 /* FIP TOC validity check */ 245 bool arm_io_is_toc_valid(void); 246 247 /* Utility functions for Dynamic Config */ 248 void arm_bl2_dyn_cfg_init(void); 249 void arm_bl1_set_mbedtls_heap(void); 250 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 251 252 #if MEASURED_BOOT 253 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 254 int arm_set_nt_fw_info( 255 /* 256 * Currently OP-TEE does not support reading DTBs from Secure memory 257 * and this option should be removed when feature is supported. 258 */ 259 #ifdef SPD_opteed 260 uintptr_t log_addr, 261 #endif 262 size_t log_size, uintptr_t *ns_log_addr); 263 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size); 264 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size); 265 #endif /* MEASURED_BOOT */ 266 267 /* 268 * Free the memory storing initialization code only used during an images boot 269 * time so it can be reclaimed for runtime data 270 */ 271 void arm_free_init_memory(void); 272 273 /* 274 * Make the higher level translation tables read-only 275 */ 276 void arm_xlat_make_tables_readonly(void); 277 278 /* 279 * Mandatory functions required in ARM standard platforms 280 */ 281 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 282 void plat_arm_gic_driver_init(void); 283 void plat_arm_gic_init(void); 284 void plat_arm_gic_cpuif_enable(void); 285 void plat_arm_gic_cpuif_disable(void); 286 void plat_arm_gic_redistif_on(void); 287 void plat_arm_gic_redistif_off(void); 288 void plat_arm_gic_pcpu_init(void); 289 void plat_arm_gic_save(void); 290 void plat_arm_gic_resume(void); 291 void plat_arm_security_setup(void); 292 void plat_arm_pwrc_setup(void); 293 void plat_arm_interconnect_init(void); 294 void plat_arm_interconnect_enter_coherency(void); 295 void plat_arm_interconnect_exit_coherency(void); 296 void plat_arm_program_trusted_mailbox(uintptr_t address); 297 bool plat_arm_bl1_fwu_needed(void); 298 __dead2 void plat_arm_error_handler(int err); 299 300 /* 301 * Optional functions in ARM standard platforms 302 */ 303 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 304 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 305 unsigned int *flags); 306 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 307 unsigned int *flags); 308 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 309 unsigned int *flags); 310 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 311 unsigned int *flags); 312 313 #if ARM_PLAT_MT 314 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 315 #endif 316 317 /* 318 * This function is called after loading SCP_BL2 image and it is used to perform 319 * any platform-specific actions required to handle the SCP firmware. 320 */ 321 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 322 323 /* 324 * Optional functions required in ARM standard platforms 325 */ 326 void plat_arm_io_setup(void); 327 int plat_arm_get_alt_image_source( 328 unsigned int image_id, 329 uintptr_t *dev_handle, 330 uintptr_t *image_spec); 331 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 332 const mmap_region_t *plat_arm_get_mmap(void); 333 334 /* Allow platform to override psci_pm_ops during runtime */ 335 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 336 337 /* Execution state switch in ARM platforms */ 338 int arm_execution_state_switch(unsigned int smc_fid, 339 uint32_t pc_hi, 340 uint32_t pc_lo, 341 uint32_t cookie_hi, 342 uint32_t cookie_lo, 343 void *handle); 344 345 /* Optional functions for SP_MIN */ 346 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 347 u_register_t arg2, u_register_t arg3); 348 349 /* global variables */ 350 extern plat_psci_ops_t plat_arm_psci_pm_ops; 351 extern const mmap_region_t plat_arm_mmap[]; 352 extern const unsigned int arm_pm_idle_states[]; 353 354 /* secure watchdog */ 355 void plat_arm_secure_wdt_start(void); 356 void plat_arm_secure_wdt_stop(void); 357 358 /* Get SOC-ID of ARM platform */ 359 uint32_t plat_arm_get_soc_id(void); 360 361 #endif /* PLAT_ARM_H */ 362