1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <assert_macros.S>
9#include <common/debug.h>
10#include <cortex_a72.h>
11#include <cpu_macros.S>
12
13	/* ---------------------------------------------
14	 * Disable all types of L2 prefetches.
15	 * ---------------------------------------------
16	 */
17func cortex_a72_disable_l2_prefetch
18	ldcopr16	r0, r1, CORTEX_A72_ECTLR
19	orr64_imm	r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20	bic64_imm	r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
21				CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK)
22	stcopr16	r0, r1, CORTEX_A72_ECTLR
23	isb
24	bx	lr
25endfunc cortex_a72_disable_l2_prefetch
26
27	/* ---------------------------------------------
28	 * Disable the load-store hardware prefetcher.
29	 * ---------------------------------------------
30	 */
31func cortex_a72_disable_hw_prefetcher
32	ldcopr16	r0, r1, CORTEX_A72_CPUACTLR
33	orr64_imm	r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34	stcopr16	r0, r1, CORTEX_A72_CPUACTLR
35	isb
36	dsb	ish
37	bx	lr
38endfunc cortex_a72_disable_hw_prefetcher
39
40	/* ---------------------------------------------
41	 * Disable intra-cluster coherency
42	 * Clobbers: r0-r1
43	 * ---------------------------------------------
44	 */
45func cortex_a72_disable_smp
46	ldcopr16	r0, r1, CORTEX_A72_ECTLR
47	bic64_imm	r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48	stcopr16	r0, r1, CORTEX_A72_ECTLR
49	bx	lr
50endfunc cortex_a72_disable_smp
51
52	/* ---------------------------------------------
53	 * Disable debug interfaces
54	 * ---------------------------------------------
55	 */
56func cortex_a72_disable_ext_debug
57	mov	r0, #1
58	stcopr	r0, DBGOSDLR
59	isb
60	dsb	sy
61	bx	lr
62endfunc cortex_a72_disable_ext_debug
63
64	/* ---------------------------------------------------
65	 * Errata Workaround for Cortex A72 Errata #859971.
66	 * This applies only to revision <= r0p3 of Cortex A72.
67	 * Inputs:
68	 * r0: variant[4:7] and revision[0:3] of current cpu.
69	 * Shall clobber: r0-r3
70	 * ---------------------------------------------------
71	 */
72func errata_a72_859971_wa
73	mov		r2,lr
74	bl		check_errata_859971
75	mov		lr, r2
76	cmp		r0, #ERRATA_NOT_APPLIES
77	beq		1f
78	ldcopr16	r0, r1, CORTEX_A72_CPUACTLR
79	orr64_imm	r1, r1, CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH
80	stcopr16	r0, r1, CORTEX_A72_CPUACTLR
811:
82	bx   		lr
83endfunc errata_a72_859971_wa
84
85func check_errata_859971
86	mov		r1, #0x03
87	b		cpu_rev_var_ls
88endfunc check_errata_859971
89
90func check_errata_cve_2017_5715
91	mov	r0, #ERRATA_MISSING
92	bx	lr
93endfunc check_errata_cve_2017_5715
94
95func check_errata_cve_2018_3639
96#if WORKAROUND_CVE_2018_3639
97	mov	r0, #ERRATA_APPLIES
98#else
99	mov	r0, #ERRATA_MISSING
100#endif
101	bx	lr
102endfunc check_errata_cve_2018_3639
103
104	/* -------------------------------------------------
105	 * The CPU Ops reset function for Cortex-A72.
106	 * -------------------------------------------------
107	 */
108func cortex_a72_reset_func
109	mov	r5, lr
110	bl	cpu_get_rev_var
111	mov	r4, r0
112
113#if ERRATA_A72_859971
114	mov	r0, r4
115	bl	errata_a72_859971_wa
116#endif
117
118#if WORKAROUND_CVE_2018_3639
119	ldcopr16	r0, r1, CORTEX_A72_CPUACTLR
120	orr64_imm	r0, r1, CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE
121	stcopr16	r0, r1, CORTEX_A72_CPUACTLR
122	isb
123	dsb	sy
124#endif
125
126	/* ---------------------------------------------
127	 * Enable the SMP bit.
128	 * ---------------------------------------------
129	 */
130	ldcopr16	r0, r1, CORTEX_A72_ECTLR
131	orr64_imm	r0, r1, CORTEX_A72_ECTLR_SMP_BIT
132	stcopr16	r0, r1,	CORTEX_A72_ECTLR
133	isb
134	bx	r5
135endfunc cortex_a72_reset_func
136
137	/* ----------------------------------------------------
138	 * The CPU Ops core power down function for Cortex-A72.
139	 * ----------------------------------------------------
140	 */
141func cortex_a72_core_pwr_dwn
142	push	{r12, lr}
143
144	/* Assert if cache is enabled */
145#if ENABLE_ASSERTIONS
146	ldcopr	r0, SCTLR
147	tst	r0, #SCTLR_C_BIT
148	ASM_ASSERT(eq)
149#endif
150
151	/* ---------------------------------------------
152	 * Disable the L2 prefetches.
153	 * ---------------------------------------------
154	 */
155	bl	cortex_a72_disable_l2_prefetch
156
157	/* ---------------------------------------------
158	 * Disable the load-store hardware prefetcher.
159	 * ---------------------------------------------
160	 */
161	bl	cortex_a72_disable_hw_prefetcher
162
163	/* ---------------------------------------------
164	 * Flush L1 caches.
165	 * ---------------------------------------------
166	 */
167	mov	r0, #DC_OP_CISW
168	bl	dcsw_op_level1
169
170	/* ---------------------------------------------
171	 * Come out of intra cluster coherency
172	 * ---------------------------------------------
173	 */
174	bl	cortex_a72_disable_smp
175
176	/* ---------------------------------------------
177	 * Force the debug interfaces to be quiescent
178	 * ---------------------------------------------
179	 */
180	pop	{r12, lr}
181	b	cortex_a72_disable_ext_debug
182endfunc cortex_a72_core_pwr_dwn
183
184	/* -------------------------------------------------------
185	 * The CPU Ops cluster power down function for Cortex-A72.
186	 * -------------------------------------------------------
187	 */
188func cortex_a72_cluster_pwr_dwn
189	push	{r12, lr}
190
191	/* Assert if cache is enabled */
192#if ENABLE_ASSERTIONS
193	ldcopr	r0, SCTLR
194	tst	r0, #SCTLR_C_BIT
195	ASM_ASSERT(eq)
196#endif
197
198	/* ---------------------------------------------
199	 * Disable the L2 prefetches.
200	 * ---------------------------------------------
201	 */
202	bl	cortex_a72_disable_l2_prefetch
203
204	/* ---------------------------------------------
205	 * Disable the load-store hardware prefetcher.
206	 * ---------------------------------------------
207	 */
208	bl	cortex_a72_disable_hw_prefetcher
209
210#if !SKIP_A72_L1_FLUSH_PWR_DWN
211	/* ---------------------------------------------
212	 * Flush L1 caches.
213	 * ---------------------------------------------
214	 */
215	mov	r0, #DC_OP_CISW
216	bl	dcsw_op_level1
217#endif
218
219	/* ---------------------------------------------
220	 * Disable the optional ACP.
221	 * ---------------------------------------------
222	 */
223	bl	plat_disable_acp
224
225	/* -------------------------------------------------
226	 * Flush the L2 caches.
227	 * -------------------------------------------------
228	 */
229	mov	r0, #DC_OP_CISW
230	bl	dcsw_op_level2
231
232	/* ---------------------------------------------
233	 * Come out of intra cluster coherency
234	 * ---------------------------------------------
235	 */
236	bl	cortex_a72_disable_smp
237
238	/* ---------------------------------------------
239	 * Force the debug interfaces to be quiescent
240	 * ---------------------------------------------
241	 */
242	pop	{r12, lr}
243	b	cortex_a72_disable_ext_debug
244endfunc cortex_a72_cluster_pwr_dwn
245
246#if REPORT_ERRATA
247/*
248 * Errata printing function for Cortex A72. Must follow AAPCS.
249 */
250func cortex_a72_errata_report
251	push	{r12, lr}
252
253	bl	cpu_get_rev_var
254	mov	r4, r0
255
256	/*
257	 * Report all errata. The revision-variant information is passed to
258	 * checking functions of each errata.
259	 */
260	report_errata ERRATA_A72_859971, cortex_a72, 859971
261	report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
262	report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
263
264	pop	{r12, lr}
265	bx	lr
266endfunc cortex_a72_errata_report
267#endif
268
269declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
270	cortex_a72_reset_func, \
271	cortex_a72_core_pwr_dwn, \
272	cortex_a72_cluster_pwr_dwn
273